Re: [PATCH v5 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The SDHC controller uses the 'default' pinctrl state for the 'sleep' state, preventing optimal power savings during suspend.
--

--- Patch [4]: [PATCH v5 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC ---
commit bac8e4df652ca68e96ed20f6144b630482c91f9a
Author: William Bright <william.bright@imd-tec.com>

arm64: dts: qcom: Add IMDT QCS8550 SBC

This commit adds the Device Tree for the IMDT QCS8550 SBC board built around
the Qualcomm QCS8550 SoC. It enables on-board regulators, uSD, UART, UFS,
PCIe0, USB, and ADSP/CDSP features.

> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts b/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts
> new file mode 100644
> index 0000000000000..fa8794868cf8e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts

[ ... ]

> +&sdhc_2 {
> +	cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
> +
> +	pinctrl-0 = <&sdc2_default>, <&sd_card_detect_default>;
> +	pinctrl-1 = <&sdc2_default>, <&sd_card_detect_default>;
> +	pinctrl-names = "default", "sleep";

[Severity: Medium]
Is it intended to reuse the active default pinctrl configuration for the sleep
state here?

Using &sdc2_default for pinctrl-1 keeps the pin drive strengths at 16mA
during system suspend. Could this cause increased current leakage and
suboptimal power savings compared to switching to a lower-power sleep state?

> +
> +	vqmmc-supply = <&sdhci_2_vqmmc>;
> +
> +	bus-width = <4>;
> +	no-sdio;
> +	no-mmc;
> +
> +	status = "okay";
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com?part=4