From: Roman Vivchar via B4 Relay <devnull+rva333.protonmail.com@kernel.org>
To: Srinivas Kandagatla <srini@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
Lala Lin <lala.lin@mediatek.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Roman Vivchar <rva333@protonmail.com>
Subject: [PATCH v2 2/3] nvmem: mtk-efuse: add support for 32-bit aligned reads
Date: Fri, 24 Jul 2026 14:07:07 +0300 [thread overview]
Message-ID: <20260724-6572-nvmem-v2-2-e58d16a29621@protonmail.com> (raw)
In-Reply-To: <20260724-6572-nvmem-v2-0-e58d16a29621@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Some MediaTek SoCs, such as mt6572, don't support 8-bit reads, leading
to zeroes or garbage data. 32-bit aligned reads must be used instead.
Introduce a 'mtk_reg_read_aligned' helper to enforce 32-bit aligned
register access. All reads will be performed by reading 4-byte words
and masking them.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/nvmem/mtk-efuse.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
index af953e1d9230..178b9d85f813 100644
--- a/drivers/nvmem/mtk-efuse.c
+++ b/drivers/nvmem/mtk-efuse.c
@@ -4,6 +4,7 @@
* Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
*/
+#include <linux/align.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
@@ -14,12 +15,37 @@
struct mtk_efuse_pdata {
bool uses_post_processing;
+ bool needs_aligned_read;
};
struct mtk_efuse_priv {
void __iomem *base;
};
+static int mtk_reg_read_aligned(void *context,
+ unsigned int reg, void *_val, size_t bytes)
+{
+ struct mtk_efuse_priv *priv = context;
+ u8 *val = _val;
+ u32 i, pos, shift, val32;
+
+ for (i = 0; i < bytes; i++, val++) {
+ pos = reg + i;
+
+ /*
+ * Read on 32-bit word boundary or if it's the first
+ * iteration
+ */
+ if (i == 0 || IS_ALIGNED(pos, 4))
+ val32 = readl(priv->base + (pos & ~3));
+
+ shift = (pos & 3) * 8;
+ *val = (val32 >> shift) & 0xff;
+ }
+
+ return 0;
+}
+
static int mtk_reg_read(void *context,
unsigned int reg, void *_val, size_t bytes)
{
@@ -82,7 +108,12 @@ static int mtk_efuse_probe(struct platform_device *pdev)
econfig.add_legacy_fixed_of_cells = true;
econfig.stride = 1;
econfig.word_size = 1;
- econfig.reg_read = mtk_reg_read;
+
+ if (pdata->needs_aligned_read)
+ econfig.reg_read = mtk_reg_read_aligned;
+ else
+ econfig.reg_read = mtk_reg_read;
+
econfig.size = resource_size(res);
econfig.priv = priv;
econfig.dev = dev;
@@ -103,10 +134,12 @@ static int mtk_efuse_probe(struct platform_device *pdev)
static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
.uses_post_processing = true,
+ .needs_aligned_read = false,
};
static const struct mtk_efuse_pdata mtk_efuse_pdata = {
.uses_post_processing = false,
+ .needs_aligned_read = false,
};
static const struct of_device_id mtk_efuse_of_match[] = {
--
2.54.0
next prev parent reply other threads:[~2026-07-24 11:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-24 11:07 [PATCH v2 0/3] nvmem: mtk-efuse: mt6572 support Roman Vivchar via B4 Relay
2026-07-24 11:07 ` [PATCH v2 1/3] dt-bindings: nvmem: mediatek: efuse: add mt6572 Roman Vivchar via B4 Relay
2026-07-24 11:37 ` sashiko-bot
2026-07-24 11:07 ` Roman Vivchar via B4 Relay [this message]
2026-07-24 11:40 ` [PATCH v2 2/3] nvmem: mtk-efuse: add support for 32-bit aligned reads sashiko-bot
2026-07-24 11:07 ` [PATCH v2 3/3] nvmem: mtk-efuse: add mt6572 support Roman Vivchar via B4 Relay
2026-07-24 11:40 ` sashiko-bot
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