From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFDC436A364; Sat, 25 Jul 2026 04:51:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784955084; cv=none; b=n/1t78w//NOnNtUdL548yLrH2LAbACZaGNv10HY+T2wadO8rhEKgs1I5t8JGdeD9193YeV8LLvBo0xCavxNn+pAh4SPAectvtc2KjNJ6lVNoVYr8L3iqWEV+JzoBlNhVNKyYCcC/n6Ii29ksojMCnx6u/coegnR00onDMsVGQVU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784955084; c=relaxed/simple; bh=Rkm4yLZkUVi1jkAlFm0cNMZPkaQrtPP2msdJ53rTp0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bo18xlqozvV7UtpMVBtWxSYWFV77GKKnfGKoy3DTp7aD05JVAJZVEE1Rfrj+cFkDrTRhQbH3eFPxQRRSTAC+QlTwVGTC5nyCmcX9L1VWdJOIyKQmvnznIHj69UZsLfDhRAGL2zF9R149Fp4AXNwA1R9j0tb2tlR1a8k5BUj7AFg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=knQSHNZu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="knQSHNZu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5A0F8C2BCFC; Sat, 25 Jul 2026 04:51:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784955084; bh=Rkm4yLZkUVi1jkAlFm0cNMZPkaQrtPP2msdJ53rTp0g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=knQSHNZuPe202s27pflHGQNgifQKNbHnZwraPtYZpbv5Up/ecjXqZLt/iruppJT7y LgHzRBAbmI4WKBxp785bFoMaCtjY+Rm97gFcfYW1EEwVse3eWGgG4ACsVn4hGG+ajn lvfj5XaeNnoLpx40T+N9OKTJwG44GaqxbTCPLGPiUQjA7w/zJjQVrsIaIzQy4Ot6ci X0FKJ9LYmJKrnSw7jnYVK5/P4+OWMwBj8vFZzp5nx73wFOP5VGahw8tK8DDrShrHd+ +i5kJx8JpjUofuheAMdDZXoE/UCMtynRMEGEdU/H6G6oIZsQdS1C0hNU3KQovznea0 KE1i51pdn6H2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A6B8C53219; Sat, 25 Jul 2026 04:51:24 +0000 (UTC) From: Cody Kang via B4 Relay Date: Sat, 25 Jul 2026 00:51:13 -0400 Subject: [PATCH RESEND 04/17] dt-bindings: soc: spacemit: allow eDP/DP PHY PLL pixel clocks on K3 APMU Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260725-k3-display-v1-4-6de34d80e86c@gmail.com> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> In-Reply-To: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784955080; l=2015; i=codykang.hk@gmail.com; s=codykang; h=from:subject:message-id; bh=To2Wz4JMP1yzDvV2UFHvJJLkK8aaYjCf2yPZVKorUr8=; b=6QpiTRJLqJK2GsKELutClre7B0hn8nkeweqRCn/Wjj3e/UhBpvTQBMwgloDKX5My4q3x3I9xa aORhJl5y09nDaAK1Y6fNjz9k5B9OvtAuzbi1wOuQ/XRjPa7ZKm6wGQN X-Developer-Key: i=codykang.hk@gmail.com; a=ed25519; pk=Osn6/cs9Su/mHHw4P19cmVc3v2FMQfiWahjsN0vEkuk= X-Endpoint-Received: by B4 Relay for codykang.hk@gmail.com/codykang with auth_id=895 X-Original-From: Cody Kang Reply-To: codykang.hk@gmail.com From: Cody Kang The APMU's eDP pixel-clock muxes select the DP PHY PLLs as parents, so the K3 syscon takes two clock inputs the other variants do not have. Gate them behind the K3 compatible instead of widening the shared clock list, so a non-K3 syscon cannot silently accept clocks it has no mux for. Signed-off-by: Cody Kang --- .../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml index d3a7c93c3c54..b8fc6632a392 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -31,14 +31,18 @@ properties: maxItems: 1 clocks: - maxItems: 4 + minItems: 4 + maxItems: 6 clock-names: + minItems: 4 items: - const: osc - const: vctcxo_1m - const: vctcxo_3m - const: vctcxo_24m + - const: edp0_pll_pxclk + - const: edp1_pll_pxclk "#clock-cells": const: 1 @@ -95,6 +99,30 @@ allOf: - clocks - clock-names - "#clock-cells" + # Only the K3 APMU exposes the two eDP/DP PHY PLL pixel clocks as extra + # inputs (parents of its eDP pixel-clock muxes); every other variant has + # the four base oscillator inputs only. + - if: + properties: + compatible: + contains: + const: spacemit,k3-syscon-apmu + then: + properties: + clocks: + minItems: 4 + maxItems: 6 + clock-names: + minItems: 4 + maxItems: 6 + else: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + minItems: 4 + maxItems: 4 additionalProperties: false -- 2.43.0