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Sun, 26 Jul 2026 13:55:23 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84e5342471dsm2066436b3a.47.2026.07.26.13.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Jul 2026 13:55:20 -0700 (PDT) From: Rosen Penev To: devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hauke Mehrtens , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] dt-bindings: bus: brcm,bus-axi: Convert binding to YAML Date: Sun, 26 Jul 2026 13:55:14 -0700 Message-ID: <20260726205518.6698-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert the Broadcom AXI bus (bcma) binding from legacy .txt format to dt-schema YAML format. This resolves dtbs_check schema validation warnings for the brcm,bus-axi compatible string across all BCM47xx and BCM53xx ARM SoC board DTBs. The schema documents the AXI bus node with its required compatible and reg properties, address/size/interrupt cell configurations, and interrupt-map for assigning IRQ numbers on BCM47xx/BCM53xx platforms where automatic detection is not available. Signed-off-by: Rosen Penev --- .../devicetree/bindings/bus/brcm,bus-axi.txt | 53 ------------- .../devicetree/bindings/bus/brcm,bus-axi.yaml | 77 +++++++++++++++++++ 2 files changed, 77 insertions(+), 53 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/brcm,bus-axi.txt create mode 100644 Documentation/devicetree/bindings/bus/brcm,bus-axi.yaml diff --git a/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt b/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt deleted file mode 100644 index edd44d802139..000000000000 --- a/Documentation/devicetree/bindings/bus/brcm,bus-axi.txt +++ /dev/null @@ -1,53 +0,0 @@ -Driver for ARM AXI Bus with Broadcom Plugins (bcma) - -Required properties: - -- compatible : brcm,bus-axi - -- reg : iomem address range of chipcommon core - -The cores on the AXI bus are automatically detected by bcma with the -memory ranges they are using and they get registered afterwards. -Automatic detection of the IRQ number is not working on -BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide -them manually through device tree. Use an interrupt-map to specify the -IRQ used by the devices on the bus. The first address is just an index, -because we do not have any special register. - -The top-level axi bus may contain children representing attached cores -(devices). This is needed since some hardware details can't be auto -detected (e.g. IRQ numbers). Also some of the cores may be responsible -for extra things, e.g. ChipCommon providing access to the GPIO chip. - -Example: - - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon { - reg = <0x00000000 0x1000>; - - gpio-controller; - #gpio-cells = <2>; - }; - }; diff --git a/Documentation/devicetree/bindings/bus/brcm,bus-axi.yaml b/Documentation/devicetree/bindings/bus/brcm,bus-axi.yaml new file mode 100644 index 000000000000..951aa139dd98 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/brcm,bus-axi.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/brcm,bus-axi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom AXI Bus with bcma driver + +maintainers: + - Hauke Mehrtens + - Rafał Miłecki + +description: | + Driver for ARM AXI Bus with Broadcom Plugins (bcma). + + The cores on the AXI bus are automatically detected by bcma with the + memory ranges they are using and they get registered afterwards. + Automatic detection of the IRQ number is not working on + BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide + them manually through device tree. Use an interrupt-map to specify the + IRQ used by the devices on the bus. The first address is just an index, + because we do not have any special register. + +properties: + compatible: + const: brcm,bus-axi + + reg: + description: IOMEM address range of chipcommon core. + maxItems: 1 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: true + interrupt-map: true + +patternProperties: + "@[0-9a-f]+$": + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon { + reg = <0x00000000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + }; -- 2.55.0