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Mon, 27 Jul 2026 07:11:39 -0700 (PDT) X-Received: by 2002:a05:6a20:d50b:b0:3c0:9c1b:d0bf with SMTP id adf61e73a8af0-3c67e0b1d30mr8680592637.74.1785161499048; Mon, 27 Jul 2026 07:11:39 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc44cb92sm53438677eec.13.2026.07.27.07.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2026 07:11:38 -0700 (PDT) From: Imran Shaik Date: Mon, 27 Jul 2026 19:40:57 +0530 Subject: [PATCH 1/6] dt-bindings: ptp: Document the TSCSS on Qualcomm Lemans and Monaco SoCs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260727-tscss-v1-1-beed14e72510@oss.qualcomm.com> References: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> In-Reply-To: <20260727-tscss-v1-0-beed14e72510@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Bjorn Andersson , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDEzNSBTYWx0ZWRfXzsM+xk035k10 AQWz98W2sOW7wwyitJBmm/di65y/0mn7cZN3hLzSTYUF8O5F4hANQgac/+dXQMZykArfhlFU0Ms 0KJqTp/wYCIeJmZ9k7h0vtbAv5xhxOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDEzNSBTYWx0ZWRfX9OZnb2PuaeAw rnNtiKOuKKLN7Bhxm1A/bLpVsVZ0rxQkD/yMaB4Ln7k6/H2Loy7iZWpzH3kpdPtFf9q8bgsEB0z D1lAS9lxwjRM7QpJChnOZ7Sf7fGWGoY8We+8TpniUacPeqH3kZrQBWzwR6tfWd7432T1l0m4U/4 Rgd/EbpDtiBaFPjdbPBnFHwUlf3NyUHPiCKOzbjPCDdlQhayZ+RorZpfttPyIPzgtITNOND4kmk YglA+a7uM+IYHa3W0XLQw1MXQ6LSSrCUtiCNXhsRZEpKf6SUH7aEJHkVzqkyYZT7KTn5Ep7hFoU qQjtYSrTA4n9WH+3qfcXWvHmJlF9c7/DDBvaYaje2yjDG3rAug7NBucPAHE3hB6mPoVWgUjmuPG 1Y6JowsKpBqd5j8XYKVsMWIQaY3C+2wGbuHwEJVW/6mgBc+4rESUpyIZLtMM7tezPq/CXaC7tee EvcmWhPY6ZgLonoUkbQ== X-Proofpoint-GUID: B004dSm7okA2GkGDNslPuL3OPp-OYopB X-Authority-Analysis: v=2.4 cv=KJ9qylFo c=1 sm=1 tr=0 ts=6a67671c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=LvIppRi0fLrXIX5vxKMA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: B004dSm7okA2GkGDNslPuL3OPp-OYopB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_04,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270135 Add Devicetree bindings for the Timestamp Counter Subsystem (TSCSS) found on Qualcomm Lemans and Monaco SoCs. TSCSS is a time synchronization subsystem composed of two main blocks: Timestamp Counter (TSC) and Event Timestamp Unit (ETU). The TSC block provides a continuously running counter used for timekeeping, while the ETU captures timestamps for external hardware event triggers. Co-developed-by: Taniya Das Signed-off-by: Taniya Das Signed-off-by: Imran Shaik --- .../devicetree/bindings/ptp/qcom,lemans-tscss.yaml | 198 +++++++++++++++++++++ 1 file changed, 198 insertions(+) diff --git a/Documentation/devicetree/bindings/ptp/qcom,lemans-tscss.yaml b/Documentation/devicetree/bindings/ptp/qcom,lemans-tscss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4cbe4b00ff7dcacbd8cc111e2b4b61ebce7104aa --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/qcom,lemans-tscss.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/qcom,lemans-tscss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Timestamp Counter Subsystem (TSCSS) on Qualcomm Lemans and Monaco SoCs + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm TSCSS is a time synchronization subsystem composed of two main + blocks - the Time Stamp Counter (TSC) and the Event Timestamp Unit (ETU). + + The TSC block is a timestamp generator that maintains a running counter used + for system timekeeping, and is functional with just the AHB and counter + clocks. + The ETU block is optional and captures TSC timestamps for external + hardware events, each ETU slice binding a slice identifier to an external + event selector. Support for the ETU block requires the additional ETU + clock along with the summary interrupt and slice subnodes. + +properties: + compatible: + oneOf: + - const: qcom,lemans-tscss + - items: + - const: qcom,monaco-tscss + - const: qcom,lemans-tscss + + reg: + maxItems: 1 + + reg-names: + items: + - const: tsc + + clocks: + minItems: 2 + items: + - description: TSC AHB configuration clock. + - description: TSC global counter clock. + - description: TSC ETU clock. + + clock-names: + minItems: 2 + items: + - const: ahb + - const: cntr + - const: etu + + interrupts: + description: Summary interrupt raised based on external event for any of the ETU slices. + maxItems: 1 + + interrupt-names: + items: + - const: etu_summary + + assigned-clocks: true + assigned-clock-rates: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^etu-slice@[0-9a-f]+$": + type: object + description: ETU slice configuration + properties: + reg: + maxItems: 1 + + pinctrl-0: true + + pinctrl-names: + items: + - const: default + + qcom,etu-event-sel: + description: Event selection value for this slice. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,etu-slice: + description: ETU slice identifier. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - reg + - qcom,etu-event-sel + - qcom,etu-slice + - pinctrl-0 + - pinctrl-names + unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +allOf: + - if: + properties: + clock-names: + contains: + const: etu + then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + required: + - interrupts + - interrupt-names + - "#address-cells" + - "#size-cells" + - ranges + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + tscss@1c80000 { + compatible = "qcom,lemans-tscss"; + reg = <0x0 0x01c80000 0x0 0x2000>; + reg-names = "tsc"; + + clocks = <&gcc GCC_TSCSS_AHB_CLK>, + <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>; + clock-names = "ahb", "cntr"; + + assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>; + assigned-clock-rates = <15625000>; + }; + }; + + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + tscss@1c80000 { + compatible = "qcom,lemans-tscss"; + reg = <0x0 0x01c80000 0x0 0x2000>; + reg-names = "tsc"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_TSCSS_AHB_CLK>, + <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>, + <&gcc GCC_TSCSS_ETU_CLK>; + clock-names = "ahb", "cntr", "etu"; + + assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>, + <&gcc GCC_TSCSS_ETU_CLK>; + assigned-clock-rates = <15625000>, <15625000>; + + interrupts = ; + interrupt-names = "etu_summary"; + + etu-slice@1c91000 { + reg = <0x0 0x01c91000 0x0 0x1000>; + pinctrl-0 = <&cci_timer0>; + pinctrl-names = "default"; + qcom,etu-event-sel = <1>; + qcom,etu-slice = <1>; + }; + + etu-slice@1c92000 { + reg = <0x0 0x01c92000 0x0 0x1000>; + pinctrl-0 = <&cci_timer1>; + pinctrl-names = "default"; + qcom,etu-event-sel = <2>; + qcom,etu-slice = <2>; + }; + }; + }; +... -- 2.34.1