From: Florian Fainelli <florian.fainelli@broadcom.com>
To: bcm-kernel-feedback-list@broadcom.com,
Rosen Penev <rosenp@gmail.com>,
devicetree@vger.kernel.org
Cc: "Florian Fainelli" <f.fainelli@gmail.com>,
"Hauke Mehrtens" <hauke@hauke-m.de>,
"Rafał Miłecki" <zajec5@gmail.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"moderated list:BROADCOM BCM5301X ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ARM: dts: BCM5301X: drop extra AXI bus ranges that break PCIe
Date: Mon, 27 Jul 2026 09:49:18 -0700 [thread overview]
Message-ID: <20260727164918.11230-1-florian.fainelli@broadcom.com> (raw)
In-Reply-To: <20260628231156.1254012-1-rosenp@gmail.com>
From: Florian Fainelli <f.fainelli@gmail.com>
On Sun, 28 Jun 2026 16:11:56 -0700, Rosen Penev <rosenp@gmail.com> wrote:
> These addresses overlap with DRAM on BCM5301X/BCM470X SoCs, causing the OF
> address translation code to route PCIe MMIO accesses through the AXI bus
> space instead of directly to memory, breaking PCIe. Remove the extra
> ranges to restore the original single-entry mapping that only covers the
> AXI peripheral register space.
>
> Assisted-by: opencode:big-pickle
> Fixes: 767012397976 ("ARM: dts: BCM5301X: Describe PCIe controllers fully")
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/fixes, thanks!
--
Florian
prev parent reply other threads:[~2026-07-27 16:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-28 23:11 [PATCH] ARM: dts: BCM5301X: drop extra AXI bus ranges that break PCIe Rosen Penev
2026-06-28 23:27 ` sashiko-bot
2026-07-03 22:17 ` Rosen Penev
2026-07-27 16:49 ` Florian Fainelli [this message]
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