From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 447D8EEBB; Wed, 29 Jul 2026 04:30:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785299452; cv=none; b=kTR1YC/PSKRHdBrbfn/qBM/dkXEiJ2YxUEUju22+jZUCx2nsLbmVEd+12MhSg1dNtJugykNKM6X0KmSh8JESpRil4MK/Po/iKgjRCpkX36HJOoqfx3X+eKmqN8pS8Znt8ZbfWLvCSN/kv4TFAXg562vLGF1uNm4OIdbTTRHQlsQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785299452; c=relaxed/simple; bh=6ZLh78q8Jaw0bAiBJiGm3g23mqhcGsqF49qC1ZG3cCU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=I9nY2BaKndkjyR9kqKnF6mlqPCnSbOFQpDfS2EOgAN4SUq9PX4Bo8lDpFemVqJUx9lkJh/nYaB8TxKtkC2H6BOgdEWAWiyxs9eKzrTuDKZIPk+xd6mzuQ1yHODA6/uD0qgge0LhJjYzvyVtri2xM7MxP+ckwgaYPO73ExPG7+Ho= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f12BCVyS; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f12BCVyS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785299451; x=1816835451; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6ZLh78q8Jaw0bAiBJiGm3g23mqhcGsqF49qC1ZG3cCU=; b=f12BCVySxte30yTOOI89Uh2ZLUGAhu8+Hu/rzInN1Y6LJ/QdFkhpaM/y ldJq+6GugZhs/dRa7uKfZI91wj6OPtYBDOSDlkBBOXPj3N4TOocDdKQdf N2orEhPHkfHtxfuHWv3vXbEP6ufDZzRlgppYnYRTtXL7dsInPPWKVxUiD Ez2AU6m8XzwKSQXU8CZw7/1l38YMX9JSozYd/xXR2r2lO4b7rnarQws4k SxdJR+0+BuHFrqk3nYQi08X6NsnLMutvJiuun97TokYHQgt+3KHjrO2dF GTd0EihO5dgI9VUUaSvA7To0sAyuNOFtjHtu+Qf/+QB0b+xTlC2fPu5VI A==; X-CSE-ConnectionGUID: B4BuE8L6TnWO95OPcfEFFQ== X-CSE-MsgGUID: ZWaCPhS6TJK1TB+xBrF68A== X-IronPort-AV: E=Sophos;i="6.25,191,1779174000"; d="scan'208";a="60446878" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2026 21:30:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 28 Jul 2026 21:30:43 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 28 Jul 2026 21:30:35 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v6 0/7] Read MAC address from SST vendor specific SFDP region Date: Wed, 29 Jul 2026 10:00:19 +0530 Message-ID: <20260729043026.1811147-1-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Some Microchip/SST QSPI flashes (e.g. the SST26VF064BEUI) are factory programmed with globally unique, write-protected EUI-48 and EUI-64 identifiers stored in a vendor-specific SFDP parameter table. On boards that have no on-board EEPROM (sama5d27_wlsom1, sama5d29 curiosity, sam9x75 curiosity) this is a reliable source for an Ethernet MAC address, instead of relying on a U-Boot-provided or random address. The series exposes the SFDP as a generic NVMEM framework with no vendor code in the SPI NOR core: - The SPI NOR core exposes the entire SFDP as a generic read-only NVMEM device, rooted at a new "sfdp" child node of the flash. - A new NVMEM layout driver (drivers/nvmem/layouts/) locates the Microchip vendor parameter table at runtime and presents the EUI-48 as a "mac-address" cell. - Arbitrary parameters can be read with a standard fixed-layout (known offset) or with an nvmem-layout parser (location discovered at runtime). Changes in v6: - 3/7 - Move the SFDP NVMEM registration from sfdp.c into core.c, since sfdp.c is only for parsing the tables;use of_get_compatible_child() instead of the open-coded child-node lookup. - 2/7, 6/7, 7/7 - Add Reviewed-by: Linus Walleij. Changes in v5: - 1/7 and 5/7 - Add R-b tags - 3/7- Rework the comments, function name and commit message.Check all the nodes (for_each_available_child) for the right compatible "jedec,sfdp" instead of node name. Changes in v4: - Rework per v3 review: remove the vendor-specific SFDP handling from the SPI NOR core; expose the whole SFDP as a generic read-only NVMEM device and move the EUI extraction into an nvmem-layout driver. - Introduce a new nvmem-layout driver to discover the vendor-table location at runtime; no offset hardcoded in the device tree. - Describe the SFDP via a dedicated "sfdp" subnode (compatible "jedec,sfdp"), which also resolves the v3 dtbs_check "Unevaluated properties ('nvmem-layout')" warning. - Reverse the stored EUI bytes into canonical MAC order. - Enable the layout in sama5_defconfig. Changes in v3: - 2/3 - add support to update the QSPI partition into 'fixed-partition' binding in sama5d27_wlsom1 - 3/3 - add nvmem-layout in qspi node for EUI48 MAC Address and nvmem cell properties for macb node in sama5d27_wlsom1 Changes in v2: - 1/3 - parse the SST vendor table, read and store the addresses into a resource - managed space. Register the addresses into NVMEM framework - 2/3 - add support to update the QSPI partition into 'fixed-partition' binding v5: https://lore.kernel.org/linux-devicetree/20260721052859.171341-1-manikandan.m@microchip.com/ Manikandan Muralidharan (7): dt-bindings: mtd: jedec,spi-nor: allow the SFDP to be exposed via NVMEM dt-bindings: nvmem: layouts: add Microchip/SST SFDP EUI layout mtd: spi-nor: sfdp: expose the SFDP as a read-only NVMEM device nvmem: layouts: add Microchip/SST SFDP EUI layout driver ARM: dts: microchip: sama5d27_wlsom1: use fixed-partitions for QSPI flash ARM: dts: microchip: sama5d27_wlsom1: read MAC address from QSPI SFDP ARM: configs: sama5: enable Microchip/SST SFDP EUI NVMEM layout .../bindings/mtd/jedec,spi-nor.yaml | 18 ++ .../layouts/microchip,sst26vf-sfdp-eui.yaml | 60 ++++++ .../bindings/nvmem/layouts/nvmem-layout.yaml | 1 + MAINTAINERS | 6 + .../dts/microchip/at91-sama5d27_wlsom1.dtsi | 61 +++--- .../dts/microchip/at91-sama5d27_wlsom1_ek.dts | 2 + arch/arm/configs/sama5_defconfig | 1 + drivers/mtd/spi-nor/core.c | 91 +++++++++ drivers/nvmem/layouts/Kconfig | 10 + drivers/nvmem/layouts/Makefile | 1 + drivers/nvmem/layouts/sst26vf-sfdp-eui.c | 182 ++++++++++++++++++ 11 files changed, 411 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/layouts/microchip,sst26vf-sfdp-eui.yaml create mode 100644 drivers/nvmem/layouts/sst26vf-sfdp-eui.c base-commit: fc02acf6ac0ccde0c805c2daa9148683cdd01ba8 -- 2.43.0