Re: [PATCH v3 1/3] arm64: dts: qcom: hamoa: Number usb_2 HS port and add M.2 endpoint stubs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The M.2 USB 2.0 endpoint stub (`usb_2_m2_ep`) is incorrectly mapped to `port@1` in the `usb_2` DWC3 controller, which violates the DWC3 OF-graph schema.
- [Low] The commit message fails to mention the addition of the PCIe endpoint stub (`pcie4_port0_ep`).
--

--- Patch [1]: [PATCH v3 1/3] arm64: dts: qcom: hamoa: Number usb_2 HS port and add M.2 endpoint stubs ---
commit 83adf4d287cf5b2273e244ab2fb06d8aa0806c46
Author: Wei Deng <wei.deng@oss.qualcomm.com>

arm64: dts: qcom: hamoa: Number usb_2 HS port and add M.2 endpoint stubs
    
Number the existing High-Speed data bus port of the usb_2 DWC3
controller as port@0, consistent with the snps,dwc3 binding convention.

Also add an empty port@1 endpoint stub (usb_2_m2_ep) for the USB 2.0
interface to M.2 peripherals, and an empty UART endpoint stub
(uart14_ep) in the uart14 serial controller, so that board DTS files
can reference these labels directly without re-entering the port
hierarchy.

> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index 4ba751a65142b..dbe1bec0258ce 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
[ ... ]
> @@ -3843,6 +3848,11 @@ pcie4_port0: pcie@0 {
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;
> +
> +				port {
> +					pcie4_port0_ep: endpoint {
> +					};
> +				};
>  			};

[Severity: Low]
This isn't a bug, but the commit message details the addition of the USB and
UART M.2 endpoint stubs without mentioning the addition of this PCIe endpoint
stub in the pcie4_port0 node.

Could the commit message be updated to mention pcie4_port0_ep as well?

[ ... ]
> @@ -5189,8 +5199,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  
>  			status = "disabled";
>  
> -			port {
> -				usb_2_dwc3_hs: endpoint {
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					usb_2_dwc3_hs: endpoint {
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					usb_2_m2_ep: endpoint {
> +					};
>  				};
>  			};

[Severity: Medium]
Does mapping the M.2 USB 2.0 endpoint stub (usb_2_m2_ep) to port@1 in the usb_2
controller violate the DWC3 OF-graph schema?

The snps,dwc3-common.yaml schema explicitly reserves port@0 for the High-Speed
(USB 2.0) bus and port@1 for the Super-Speed (USB 3.0) bus.

Since the usb_2 controller is a High-Speed-only controller, attaching a USB 2.0
interface to port@1 incorrectly models the hardware by attaching it to a
non-existent SuperSpeed port.

Could this cause dtbs_check validation failures or incorrect OF-graph parsing
in drivers that expect port@1 to strictly represent a SuperSpeed link?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260729-hamoa-m2-dts-v2-v3-0-4d7ef9274575@oss.qualcomm.com?part=1