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Wed, 29 Jul 2026 09:39:25 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-496c45b0535sm164242145e9.4.2026.07.29.09.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2026 09:39:25 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, guodong@riscstar.com, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Date: Thu, 30 Jul 2026 00:39:05 +0800 Message-ID: <20260729163908.249838-1-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add device tree bindings for RISC-V Worlds, a standard extension that tags every transaction with a World ID for fine-grained isolation. SiFive's WorldGuard Checker is a hardware firewall in the system interconnect that inspects transaction WIDs and enforces per-World access policies on memory and MMIO devices. wgChecker specification reference: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf Yu-Chien Peter Lin (3): dt-bindings: riscv: Add Worlds ISA extensions dt-bindings: riscv: Add Worlds per-hart properties dt-bindings: sifive: Add WorldGuard Checker .../devicetree/bindings/riscv/cpus.yaml | 61 +++ .../devicetree/bindings/riscv/extensions.yaml | 53 +++ .../devicetree/bindings/riscv/worlds.yaml | 86 +++++ .../bindings/sifive/sifive,wgchecker2.yaml | 356 ++++++++++++++++++ 4 files changed, 556 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml -- 2.43.7