From: sashiko-bot@kernel.org
To: "Aurelien Jarno" <aurelien@aurel32.net>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v2 3/4] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board
Date: Wed, 29 Jul 2026 17:33:31 +0000 [thread overview]
Message-ID: <20260729173332.51D661F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260729172450.1660418-4-aurelien@aurel32.net>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Mismatch between the length of the `phys` and `phy-names` properties in the `usb3b` and `usb3c` device tree nodes.
--
--- Patch [3]: [PATCH v2 3/4] riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board ---
commit 2aa9a6448bde1ee249cba54ddbed1021d4ace1cc
Author: Aurelien Jarno <aurelien@aurel32.net>
riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board
This commit adds the USB3 B and C controller nodes and their corresponding
USB2 and USB3 PHY nodes to the SpacemiT K3 SoC device tree. It also enables
them on the K3 Pico-ITX board in USB 2 mode.
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 0eb24fac4733e..b786f119d4f95 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
[ ... ]
> + usb3b: usb@81400000 {
> + compatible = "spacemit,k3-dwc3";
> + reg = <0x0 0x81400000 0x0 0x10000>;
[ ... ]
> + resets = <&syscon_apmu RESET_APMU_USB3_B_AHB>,
> + <&syscon_apmu RESET_APMU_USB3_B_VCC>,
> + <&syscon_apmu RESET_APMU_USB3_B_PHY>;
> + reset-names = "ahb", "vcc", "phy";
> + phys = <&usb3b_u2phy>,
> + <&combophy 2 PHY_TYPE_USB3>;
> + phy-names = "usb2-phy";
[Severity: Medium]
Does this mismatch between the array lengths of phys and phy-names cause
dtbs_check schema validation to fail? The phys property defines two items,
but phy-names only lists "usb2-phy", omitting "usb3-phy".
Without "usb3-phy" in the phy-names list, devm_phy_get(dev, "usb3-phy")
in the DWC3 core driver will fail. While the current Pico-ITX board limits
this controller to high-speed mode, does this omission bypass USB3 PHY
initialization and break SuperSpeed functionality for any future generic
boards using this SoC-level .dtsi?
> + phy_type = "utmi";
[ ... ]
> + usb3c: usb@81700000 {
> + compatible = "spacemit,k3-dwc3";
> + reg = <0x0 0x81700000 0x0 0x10000>;
[ ... ]
> + resets = <&syscon_apmu RESET_APMU_USB3_C_AHB>,
> + <&syscon_apmu RESET_APMU_USB3_C_VCC>,
> + <&syscon_apmu RESET_APMU_USB3_C_PHY>;
> + reset-names = "ahb", "vcc", "phy";
> + phys = <&usb3c_u2phy>,
> + <&combophy 3 PHY_TYPE_USB3>;
> + phy-names = "usb2-phy";
[Severity: Medium]
Similarly here, does omitting "usb3-phy" from the phy-names array also
break USB3 PHY power-on and initialization for the usb3c controller on
future boards?
> + phy_type = "utmi";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260729172450.1660418-1-aurelien@aurel32.net?part=3
next prev parent reply other threads:[~2026-07-29 17:33 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260729172450.1660418-1-aurelien@aurel32.net>
2026-07-29 17:20 ` [PATCH v2 2/4] riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX board Aurelien Jarno
2026-07-29 17:20 ` [PATCH v2 3/4] riscv: dts: spacemit: k3: add USB3 B and C controllers for " Aurelien Jarno
2026-07-29 17:33 ` sashiko-bot [this message]
2026-07-29 17:20 ` [PATCH v2 4/4] riscv: dts: spacemit: k3: add rfkill node for WLAN Aurelien Jarno
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