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Thu, 30 Jul 2026 10:54:44 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13e72643a12sm36444098c88.5.2026.07.30.10.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 10:54:43 -0700 (PDT) From: Taniya Das Subject: [PATCH v4 0/5] clk: qcom: Introduce initial clock controllers for Maili SoC Date: Thu, 30 Jul 2026 23:24:33 +0530 Message-Id: <20260730-maili_initial_clock-v4-0-ed52ade264f0@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIANmPa2oC/3XNTQ6CMBAF4KuYri3pLwVX3sMYQkuRiYUqRaIh3 N1CYnSBm0ne5M03Ewq2BxvQYTeh3o4QwHcxiP0OmabsLhZDFTNihKUkpQq3JTgooIMBSlcY580 VG2WZFpKTKiMoXt56W8NzVU/nmBsIg+9f65ORLtuPl216I8UEV6mtLOGSUcqPPoTk/iid8W2bx IEWdmRfSlG+TbFIqVyKrCZay6z+Q/EfioltikdKSC1VbFCT0w1qnuc3oPmcrlMBAAA= X-Change-ID: 20260617-maili_initial_clock-c7e2b4530d80 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Vivek Aknurwar Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDEzMyBTYWx0ZWRfX3KiHbOiLNOCv 3ISs3G9JH09oBtZ98fYPg2UeVWVJjf9D0n/x4AvEPOOgYel4vMIvo/HDAqm9ji2CNQI0+eZqvTt LZlzT5PKN1YURdLyjOIIZpWlu3mcmnaJ7KiYIYo/DH8IdiIhY3k5TXq0Pb/4MIgq93D/FZefakj 8iN3NVqYZvsJHB8TMYZfVAoIMKiBAloJAp9BYGjQQG36nycQF/JLG6nvUet3CK7+c8JutaZoQjm f738dniBGAxsERYxrYT9dSykYyJ9UlgiuyyG2b1jGtQQ2c4uva8XxTwAllgmyng9wJTd0H73Z8X czfqmF+fTe1vfSxreUQK+8OyjyXUq6wrhFQKvuGmM74vgaqiLyALSh8iL+iBCqF6shTS4S070Tf de6yiUfovRc17n3xPNjbucZ2uAq+OxBFLe4qbHwceaHz5DCwQAkzWiOhIvTMTBAnLqfHV52Jjx8 EDWr2XK6YKLb2P/KDnw== X-Authority-Analysis: v=2.4 cv=DNq/JSNb c=1 sm=1 tr=0 ts=6a6b8fe5 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Kp3T8kGXBi3sce7iFlAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: fWs0_Tfd60jOQ7aZB9btwrUqiF1B-i5b X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDEzMyBTYWx0ZWRfXwKMsFNDgYDNW sNWWLC8QKBkr5HAbUFCIajQ+b8GCPrKgINY/ytsFPgv6/4002z3RrqyaTWImRNWZG6cgADnrH95 /LzqgRtlzn8Azge0jSo+8K7HoJ9IC9s= X-Proofpoint-GUID: fWs0_Tfd60jOQ7aZB9btwrUqiF1B-i5b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300133 Introduce the initial set of clock controller bindings and driver support for the upcoming Qualcomm Maili SoC. Maili is a new mobile SoC from Qualcomm. It is a derivative of the Hawi SoC and shares most of its clock topology. Where the hardware is identical, Maili reuses the existing Hawi drivers via fallback compatible strings. Where Maili diverges — specifically in the Global Clock Controller (GCC), which carries an additional QUPv3 wrapper (WRAP5) — the Hawi GCC driver is extended to handle both SoCs. The series covers the following clock controllers: - RPMH clock controller: identical to Hawi; uses qcom,hawi-rpmh-clk as fallback. - TCSR clock controller: identical to Hawi; uses qcom,hawi-tcsrcc as fallback. - Global Clock Controller (GCC): extends the Hawi GCC driver with eight additional QUPV3 WRAP5 clocks present only on Maili. - CPUCP mailbox controller: software-compatible with X1E80100; uses qcom,x1e80100-cpucp-mbox as fallback. The devicetree for Maili will be upstreamed later. Changes in v4: - Rebase the binding of tcsr to linux-next. - Add RB-by from Konrad Dybcio on the GCC driver patch. - Link to v3: https://lore.kernel.org/r/20260724-maili_initial_clock-v3-0-45b577241c91@oss.qualcomm.com Changes in v3: - Update the comment for extending the array appropriately size. - Add RB-by [Krzysztof] from v2 - Link to v2: https://lore.kernel.org/r/20260713-maili_initial_clock-v2-0-79548f0bb58f@oss.qualcomm.com Changes in v2: - Split the new Maili-only QUPv3 WRAP5 clock IDs out of qcom,hawi-gcc.h into a new qcom,maili-gcc.h header (which includes qcom,hawi-gcc.h), instead of adding them directly to the Hawi header. [Krzysztof] - Update the GCC driver to include the maili-gcc header. - Link to v1: https://lore.kernel.org/r/20260618-maili_initial_clock-v1-0-d6ede0352113@oss.qualcomm.com --- Taniya Das (5): dt-bindings: clock: qcom-rpmhcc: Add RPMH clock controller for Maili dt-bindings: clock: qcom: Add Maili TCSR clock controller dt-bindings: clock: qcom: Add Maili global clock controller clk: qcom: gcc-hawi: Add support for global clock controller on Maili dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller .../devicetree/bindings/clock/qcom,hawi-gcc.yaml | 11 +- .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 65 ++++--- .../bindings/clock/qcom,sm8550-tcsr.yaml | 32 ++-- .../bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + drivers/clk/qcom/gcc-hawi.c | 201 +++++++++++++++++++++ include/dt-bindings/clock/qcom,maili-gcc.h | 21 +++ 6 files changed, 285 insertions(+), 46 deletions(-) --- base-commit: 95d6a9ccef99117115e41e9adb271243bd5e985b change-id: 20260617-maili_initial_clock-c7e2b4530d80 Best regards, -- Taniya Das