On Wed, Jul 29, 2026 at 04:40:00PM -0500, David Lechner wrote:
> On 7/29/26 3:47 PM, Conor Dooley wrote:
> 
> ...
> 
> > Only going to reply to this for now, I'll reply to the other thread of
> > this conversation later so as not to end up duplicating discussion, but
> > I am thinking of things like what if someone puts a mcp3654r and an
> > ad5529r on the same chip select? I think that's actually perfectly
> > functional on a hardware level, provided the fuses/pins are set up
> I'm not sure this works in general since SPI devices aren't going to
> have a standard way to specify the address.
> 
> For example, ad5529r has the address at bits [14:12] in a 16-bit
> "instruction phase" while mcp3654r has the address at [7:6] in the
> "command byte".
> 
> An ad5529r instruction could inadvertently be interpreted as a
> command by mcp3654r. So I don't think they could exist on the
> same CS.

Yeah, actually you're right. I didn't notice that the ID bits weren't
the first two on the bus for the ADI device.

> 
> > correctly (and if it is not, mixing the microchip devices is possible
> > and probably mixing future ADI ones will be too).
> > 
> 
> Yes, I suppose this could be possible, but I don't think they would
> be considered a single logical device in that case. So would be
> covered by the device@cs,spi-addr binding that we already discussed.

Right, that is what I was thinking - I just don't really want to
entertain supporting both this and the "single logical device"
configuration for the same device.

> 
> Example:
> 
> adc@0,0 {
>     compatible = "adi,adc1";
>     ...
> };
> 
> adc@0,1 {
>     compatible = "adi,adc2";
>     ...
> };