Re: [PATCH v4 3/5] dt-bindings: clock: qcom: Add Maili global clock controller

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing QUPV3 WRAP5 reset definition (e.g., GCC_QUPV3_WRAPPER_5_BCR) for the Maili GCC.
--

--- Patch [3]: [PATCH v4 3/5] dt-bindings: clock: qcom: Add Maili global clock controller ---
commit 833adf32860ecbd5cd7a72269cd3221a4b141fad
Author: Taniya Das <taniya.das@oss.qualcomm.com>

dt-bindings: clock: qcom: Add Maili global clock controller

This commit adds device tree bindings for the global clock controller (GCC)
on the Qualcomm Maili SoC. It extends the existing Hawi GCC bindings and
introduces a new header file for the Maili-specific clocks.

> diff --git a/include/dt-bindings/clock/qcom,maili-gcc.h b/include/dt-bindings/clock/qcom,maili-gcc.h
> new file mode 100644
> index 0000000000000..9bea90adb988e
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,maili-gcc.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_MAILI_H
> +
> +#include "qcom,hawi-gcc.h"
> +
> +/* Maili has below additional clocks on top of Hawi */
> +#define GCC_QUPV3_WRAP5_CORE_2X_CLK				188
> +#define GCC_QUPV3_WRAP5_CORE_CLK				189
> +#define GCC_QUPV3_WRAP5_QSPI_REF_CLK				190

[Severity: Medium]
Does the QUPv3 WRAP5 hardware on Maili also require a corresponding reset
definition (such as GCC_QUPV3_WRAPPER_5_BCR)?

The QUPv3 core driver usually needs a reset for each wrapper to initialize
it and recover from hardware errors. Without the reset index macro included
here alongside the clocks, it looks like developers won't be able to define
the resets property for WRAP5 in the Device Tree.

> +#define GCC_QUPV3_WRAP5_QSPI_REF_CLK_SRC			191
> +#define GCC_QUPV3_WRAP5_S0_CLK					192
> +#define GCC_QUPV3_WRAP5_S0_CLK_SRC				193
> +#define GCC_QUPV3_WRAP_5_M_AHB_CLK				194
> +#define GCC_QUPV3_WRAP_5_S_AHB_CLK				195
> +
> +#endif

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-maili_initial_clock-v4-0-ed52ade264f0@oss.qualcomm.com?part=3