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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2db9ba855sm638689e87.49.2026.07.30.16.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 16:53:59 -0700 (PDT) From: Dmitry Baryshkov To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal , Bryan O'Donoghue , Konrad Dybcio Subject: [PATCH v9 15/19] media: iris: implement support for the Agatti platform Date: Fri, 31 Jul 2026 02:53:59 +0300 Message-ID: <20260731-iris-ar50lt-v9-15-d71a782001c0@oss.qualcomm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> References: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23999; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=6OjKQrilXN0APkalyYq6SzYOs+r0hfC+Yg8l6pjrRd8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqa+Mt7Dkq6gVl/v5PeWxWvtSBVX6WCxYe9nLRr BJtFcLiEDOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCamvjLQAKCRCLPIo+Aiko 1YU2B/9DbHBjtefu59R19U7Kx0pZRlBH3tpCFC270SoNkGKBs5Ydw+zsNMSakEHdWRiKnU9k9WZ 9tK2PI5caL5sKIODdIlZawgf9GYlTPos+VfUZipe9EIm0endc5j9u7gcOsFMmms0Q4Aj63oRPnM uC4IfXLPx5uzOJwshpAdvnh9DSvV+qhnvQ8W5wlwvDp1HLwrZ8TewOiknOme9/PdRUjSWh3hGe/ plYjz4RKVggnRDMVxhExT/JGEyPvwvecm6hm4QP5WVj4kvrJSTPJLgthkWlYqdjIVB5ihYuzcrV qyXR2fvJLYNYmWX3o7iZiWY7Dco7S7MWLp5N041rtMj9dj3q X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfXxoUyYICHfxRs Jq8bRLJRQBzdAspCXPC4WQie6+ufK/V8XURPQVxG9o1fLzYKhZz2GymZz2TGhyI21V7A0iM1y3I t9eihpLVuY2suACU+NeRHNmvgIS6zo0= X-Proofpoint-GUID: 7jui78YKd1M0xhcYj48ZwyaahDxHjudt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfX+D//1sKnmYAI 5rDr1jCehTpUzdadmCaoD5JFIkTKtGKFoJW2A8kMx38vrMVDN0umVH5yvMjRkbdEpEU6akVin1V G9MFr62Gyxw1k4NCL3ZBQ8LgHDmoytWPhhj359laQS7sa/rROUEAacnCzH7Z59OBAC+/Mr9uNVm thuqNz7ZX4I0LtGFSg57vFQA1Pz220FMpNnqPjIPDXH4T6BrwsTahf9u/8b94lcrHq0JcGynwuW eoAIAaleEa5TERTtnYtiHdPFzavoGGIaPrFoWAe7JGNIJCmbjiftXqC0YmiTSF779mcQ9eRGej1 v/fEmF1g+Xpm3CKXrcJRfBYqW/Fi7VXREBbO2I7FWh9RUq964ah+6iXb5Y8i1wwzuP0AxYTplMC 6nwyhkc1ijhrMww9T4xX1Au/OZWQKk1RwNXCrH4+1Zc4Vn/pHfmT3wRBF/WfYzT38u0OvanUuV6 roNEYR1gdZvi+KTpOKg== X-Authority-Analysis: v=2.4 cv=N+kZ0W9B c=1 sm=1 tr=0 ts=6a6be41b cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=CzQNLXtIClULElcFgiYA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: 7jui78YKd1M0xhcYj48ZwyaahDxHjudt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_07,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300168 Port support for the AR50Lt video codec core (present for example on the Agatti platform) to the Iris driver. Unlike more recent cores this generation doesn't have the PIPE property (as it always has only one pipe). Also, unlike newer platforms, buffer sizes are requested from the firmware instead of being calculated by the driver. Co-developed-by: Dikshita Agarwal Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 404 +++++++++++++++++++++ .../platform/qcom/iris/iris_hfi_gen1_command.c | 9 + .../platform/qcom/iris/iris_platform_common.h | 9 + .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 110 ++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 5 + drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 + 8 files changed, 543 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index f1b204b95694..bbd1f724963e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -14,6 +14,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_queue.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ + iris_platform_vpu_ar50lt.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 0f7e7d6b25f4..548609315b85 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -445,3 +445,407 @@ const struct iris_firmware_data iris_hfi_gen1_data = { .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +static const struct platform_inst_fw_cap iris_inst_fw_cap_gen1_ar50lt_dec[] = { + { + .cap_id = STAGE, + .min = STAGE_1, + .max = STAGE_2, + .step_or_mask = 1, + .value = STAGE_2, + .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE, + .set = iris_set_stage, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_gen1_ar50lt_enc[] = { + { + .cap_id = STAGE, + .min = STAGE_1, + .max = STAGE_2, + .step_or_mask = 1, + .value = STAGE_2, + .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE, + .set = iris_set_stage, + }, + { + .cap_id = PROFILE_H264, + .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH), + .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_profile_level_gen1, + }, + { + .cap_id = PROFILE_HEVC, + .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_profile_level_gen1, + }, + { + .cap_id = LEVEL_H264, + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_profile_level_gen1, + }, + { + .cap_id = LEVEL_HEVC, + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_profile_level_gen1, + }, + { + .cap_id = HEADER_MODE, + .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_header_mode_gen1, + }, + { + .cap_id = BITRATE, + .min = BITRATE_MIN, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = BITRATE_STEP, + .value = BITRATE_DEFAULT_AR50LT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = BITRATE_MODE, + .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id = HFI_PROPERTY_PARAM_VENC_RATE_CONTROL, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_bitrate_mode_gen1, + }, + { + .cap_id = FRAME_SKIP_MODE, + .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id = FRAME_RC_ENABLE, + .min = 0, + .max = 1, + .step_or_mask = 1, + .value = 1, + }, + { + .cap_id = GOP_SIZE, + .min = 0, + .max = (1 << 16) - 1, + .step_or_mask = 1, + .value = 30, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_intra_period, + }, + { + .cap_id = ENTROPY_MODE, + .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .hfi_id = HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set = iris_set_entropy_mode_gen1, + }, + { + .cap_id = MIN_FRAME_QP_H264, + .min = MIN_QP_8BIT_AR50LT, + .max = MAX_QP, + .step_or_mask = 1, + .value = MIN_QP_8BIT_AR50LT, + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_qp_range, + }, + { + .cap_id = MIN_FRAME_QP_HEVC, + .min = MIN_QP_8BIT_AR50LT, + .max = MAX_QP_HEVC, + .step_or_mask = 1, + .value = MIN_QP_8BIT_AR50LT, + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_qp_range, + }, + { + .cap_id = MAX_FRAME_QP_H264, + .min = MIN_QP_8BIT_AR50LT, + .max = MAX_QP, + .step_or_mask = 1, + .value = MAX_QP, + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_qp_range, + }, + { + .cap_id = MAX_FRAME_QP_HEVC, + .min = MIN_QP_8BIT_AR50LT, + .max = MAX_QP_HEVC, + .step_or_mask = 1, + .value = MAX_QP_HEVC, + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_qp_range, + }, + { + .cap_id = IR_TYPE, + .min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, + .step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) | + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC), + .value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id = IR_PERIOD, + .min = 0, + .max = ((4096 * 2304) >> 8), + .step_or_mask = 1, + .value = 0, + .hfi_id = HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_ir_period_gen1, + }, + { + .cap_id = LTR_COUNT, + .min = 0, + .max = MAX_LTR_FRAME_COUNT_GEN1, + .step_or_mask = 1, + .value = 0, + .hfi_id = HFI_PROPERTY_PARAM_VENC_LTRMODE, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_ltr_count_gen1, + }, + { + .cap_id = USE_LTR, + .min = 0, + .max = ((1 << MAX_LTR_FRAME_COUNT_GEN1) - 1), + .step_or_mask = 0, + .value = 0, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_USELTRFRAME, + .flags = CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_use_ltr, + }, + { + .cap_id = MARK_LTR, + .min = 0, + .max = (MAX_LTR_FRAME_COUNT_GEN1 - 1), + .step_or_mask = 1, + .value = 0, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME, + .flags = CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_mark_ltr, + }, + { + .cap_id = B_FRAME, + .min = 0, + .max = 3, + .step_or_mask = 1, + .value = 0, + .flags = CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id = LAYER_ENABLE, + .min = 0, + .max = 1, + .step_or_mask = 1, + .value = 0, + .flags = CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id = LAYER_TYPE_H264, + .min = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .max = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P), + .value = V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id = LAYER_COUNT_H264, + .min = 0, + .max = MAX_HIER_CODING_LAYER_GEN1, + .step_or_mask = 1, + .value = 0, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER, + .flags = CAP_FLAG_OUTPUT_PORT, + .set = iris_set_layer_count_gen1, + }, + { + .cap_id = LAYER0_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = LAYER1_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = LAYER2_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = LAYER3_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = LAYER4_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = LAYER5_BITRATE_H264, + .min = 1, + .max = BITRATE_MAX_AR50LT, + .step_or_mask = 1, + .value = BITRATE_DEFAULT, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_bitrate_gen1, + }, + { + .cap_id = REQUEST_SYNC_FRAME, + .min = 0, + .max = 1, + .step_or_mask = 1, + .value = 0, + .hfi_id = HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME, + .flags = CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set = iris_set_req_sync_frame, + }, +}; + +static const u32 iris_hfi_gen1_ar50lt_dec_ip_int_buf_tbl[] = { + BUF_BIN, + BUF_SCRATCH_1, +}; + +/* + * Unlike sm8250, on AR50Lt the internal buffer sizes are provided by the + * firmware. Request HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL so that the encoder + * queries HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS before allocating them. + */ +static const u32 iris_hfi_gen1_ar50lt_venc_input_config_param[] = { + HFI_PROPERTY_CONFIG_FRAME_RATE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO, + HFI_PROPERTY_PARAM_FRAME_SIZE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, + HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, + HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, +}; + +const struct iris_firmware_data iris_hfi_gen1_ar50lt_data = { + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init, + + .query_buffer_requirements = true, + + .inst_fw_caps_dec = iris_inst_fw_cap_gen1_ar50lt_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(iris_inst_fw_cap_gen1_ar50lt_dec), + .inst_fw_caps_enc = inst_fw_cap_gen1_ar50lt_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc), + + .dec_input_config_params_default = + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params = iris_hfi_gen1_ar50lt_venc_input_config_param, + .enc_input_config_params_size = + ARRAY_SIZE(iris_hfi_gen1_ar50lt_venc_input_config_param), + + .dec_ip_int_buf_tbl = iris_hfi_gen1_ar50lt_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(iris_hfi_gen1_ar50lt_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 5650645f9f65..47e9147a9b6d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -973,6 +973,13 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane) struct hfi_buffer_size_actual bufsz; int ret; + if (inst->core->iris_firmware_data->query_buffer_requirements) { + ret = inst->hfi_session_ops->session_get_property(inst, + HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS); + if (ret) + return ret; + } + if (iris_split_mode_enabled(inst)) { bufsz.type = HFI_BUFFER_OUTPUT; bufsz.size = inst->core->iris_firmware_desc->get_vpu_buffer_size(inst, BUF_DPB); @@ -1087,6 +1094,8 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p iris_hfi_gen1_set_raw_format}, {HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, iris_hfi_gen1_set_num_bufs}, + {HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, + iris_hfi_gen1_set_bufsize}, }; if (inst->domain == DECODER) { diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 4ed0709ec381..07cd02d6bfc8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -39,6 +39,10 @@ struct iris_inst; #define MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW 5 #define MAX_HIER_CODING_LAYER_GEN1 6 +#define BITRATE_MAX_AR50LT 100000000 +#define BITRATE_DEFAULT_AR50LT 20000000 +#define MIN_QP_8BIT_AR50LT 0 + enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -51,10 +55,12 @@ enum pipe_type { }; extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data; extern const struct iris_firmware_data iris_hfi_gen2_data; extern const struct iris_firmware_data iris_hfi_milos_data; extern const struct iris_platform_data milos_data; +extern const struct iris_platform_data qcm2290_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; @@ -245,6 +251,9 @@ struct iris_firmware_data { u32 core_arch; + /* Query buffer sizes from the firmware (pre-Iris HFI Gen1 platforms). */ + bool query_buffer_requirements; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c new file mode 100644 index 000000000000..92f7e2546539 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10 + +static const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc = { + .firmware_data = &iris_hfi_gen1_ar50lt_data, + .get_vpu_buffer_size = iris_vpu_ar50lt_gen1_buf_size, + .fwname = "qcom/venus-6.0/venus.mbn", +}; + +static const u32 iris_fmts_ar50lt_dec[] = { + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, +}; + +static const struct bw_info iris_bw_table_dec_ar50lt[] = { + { ((1920 * 1080) / 256) * 60, 1564000, }, + { ((1920 * 1080) / 256) * 30, 791000, }, + { ((1280 * 720) / 256) * 60, 688000, }, + { ((1280 * 720) / 256) * 30, 347000, }, +}; + +static const struct icc_info iris_icc_info_ar50lt[] = { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 6500000 }, +}; + +static const char * const iris_pmdomain_table_ar50lt[] = { "venus", "vcodec0" }; + +static const char * const iris_opp_pd_table_ar50lt[] = { "cx" }; + +static const struct platform_clk_data iris_clk_table_ar50lt[] = { + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_HW_AHB_CLK, "vcodec0_bus" }, + {IRIS_THROTTLE_CLK, "throttle" }, +}; + +static const char * const iris_opp_clk_table_ar50lt[] = { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_ar50lt[] = { + { + .cp_start = 0, + .cp_size = 0x25800000, + .cp_nonpixel_start = 0x01000000, + .cp_nonpixel_size = 0x24800000, + }, +}; + +static struct platform_inst_caps platform_inst_cap_ar50lt = { + .min_frame_width = 128, + .max_frame_width = 1920, + .min_frame_height = 128, + .max_frame_height = 1920, + .max_mbpf = (1920 * 1088) / 256, + .mb_cycles_vpp = 440, + .mb_cycles_fw = 733003, + .mb_cycles_fw_vpp = 225975, + .max_frame_rate = 120, + .max_operating_rate = 120, +}; + +const struct iris_platform_data qcm2290_data = { + .firmware_desc_gen1 = &iris_vpu_ar50lt_p1_gen1_s6_desc, + .vpu_ops = &iris_vpu_ar50lt_ops, + .icc_tbl = iris_icc_info_ar50lt, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_ar50lt), + .bw_tbl_dec = iris_bw_table_dec_ar50lt, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_ar50lt), + .pmdomain_tbl = iris_pmdomain_table_ar50lt, + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_ar50lt), + .opp_pd_tbl = iris_opp_pd_table_ar50lt, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_ar50lt), + .clk_tbl = iris_clk_table_ar50lt, + .clk_tbl_size = ARRAY_SIZE(iris_clk_table_ar50lt), + .opp_clk_tbl = iris_opp_clk_table_ar50lt, + /* Upper bound of DMA address range */ + .dma_mask = 0xe0000000 - 1, + .inst_iris_fmts = iris_fmts_ar50lt_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_ar50lt_dec), + .inst_caps = &platform_inst_cap_ar50lt, + .tz_cp_config_data = tz_cp_config_ar50lt, + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_ar50lt), + .num_vpp_pipe = 1, + .no_rpmh = true, + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier = 2, + .max_session_count = 8, + .max_core_mbpf = ((1920 * 1088) / 256) * 4, + /* Concurrency: 1080p@30 decode + 1080p@30 encode */ + /* Concurrency: 3 * 1080p@30 decode */ + .max_core_mbps = (((1920 * 1088) / 256) * 90), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 5db6398433a4..5adb9dfb70fc 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -362,6 +362,10 @@ static const struct of_device_id iris_dt_match[] = { .compatible = "qcom,milos-iris", .data = &milos_data, }, + { + .compatible = "qcom,qcm2290-venus", + .data = &qcm2290_data, + }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c index faebb5472866..83dc4a1db954 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -2194,6 +2194,11 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ return size; } +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) +{ + return inst->buffers[buffer_type].size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h index 8c0d6b7b5de8..1d07137c70cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -288,6 +288,7 @@ static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height) u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type); int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type); #endif -- 2.47.3