Re: [PATCH v2 2/4] dt-bindings: iio: adc: adi,ade9000: add adi,ade9078 compatible

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] The IIO channels for Phase B and Phase C have overlapping `scan_index` values, causing them to conflict in the IIO buffer and preventing correct channel configuration.
- [High] The IRQ1 handler loop stops at bit 24, completely ignoring Phase C dip events (`ADE9000_ST1_DIPC_BIT`) which are located at bit 25.
--

--- Patch [2]: [PATCH v2 2/4] dt-bindings: iio: adc: adi,ade9000: add adi,ade9078 compatible ---
commit fea768d482e94a570394d820d69e5c756bc56362
Author: Antoniu Miclaus <antoniu.miclaus@analog.com>

dt-bindings: iio: adc: adi,ade9000: add adi,ade9078 compatible

This commit adds the ADE9078 compatible string to the ADE9000 binding and
lowers the maximum spi frequency for the new variant.

> The ADE9078 is a polyphase energy metering device from the same family as
> the ADE9000. It is register-compatible with the ADE9000 but does not
> provide the on-chip dip/swell detection and is limited to a 10 MHz SPI
> clock.

[Severity: High]
This isn't a bug introduced by this patch, but while reviewing the ADE9000
driver family, I noticed a potential conflict with the channel
configurations.

Looking at drivers/iio/adc/ade9000.c:

#define ADE9000_CURRENT_CHANNEL(num) { \
...
	.scan_index = num,
...
#define ADE9000_VOLTAGE_CHANNEL(num) { \
...
	.scan_index = num + 1, /* interleave with current channels */

Does this cause Phase A Voltage (index 1) to conflict with Phase B Current
(index 1), and Phase B Voltage (index 2) to conflict with Phase C Current
(index 2)?

When a user enables Phase B or C channels via sysfs, it seems this could
cause the active_scan_mask to map to the wrong bits. Could this lead to
an unsupported combination of scans or incorrect channel configuration in
ade9000_waveform_buffer_config():

	bitmap_to_arr32(&active_scans, indio_dev->active_scan_mask,
			iio_get_masklength(indio_dev));

	switch (active_scans) {
	case ADE9000_SCAN_POS_IA | ADE9000_SCAN_POS_VA:


[Severity: High]
This is also a pre-existing issue, but I noticed a potential problem with
the Phase C dip detection logic.

Looking at drivers/iio/adc/ade9000.c:

#define ADE9000_ST1_CROSSING_DEPTH	25
...
#define ADE9000_ST1_DIPC_BIT		BIT(25)

And later in ade9000_irq1_thread():

	bitmap_from_arr32(interrupt_bits, &interrupts, ADE9000_ST1_CROSSING_DEPTH);
	for_each_set_bit_from(bit, interrupt_bits,
			      ADE9000_ST1_CROSSING_DEPTH) {
		tmp = status & BIT(bit);

Since ADE9000_ST1_CROSSING_DEPTH is 25, will these operations only handle
bits 0 through 24? Does this mean bit 25 is missed and Phase C dip events
are silently ignored when the hardware triggers an IRQ1?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260731082951.1228-1-antoniu.miclaus@analog.com?part=2