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Mon, 03 Aug 2026 04:21:19 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd458adc9sm34154913f8f.27.2026.08.03.04.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:21:18 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 0/5] arm64: dts: nuvoton: add NPCM845 SoC and EVB support Date: Mon, 3 Aug 2026 14:19:01 +0300 Message-Id: <20260803111906.1931384-1-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series fixes the remaining timer binding issue and adds device tree support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation Board (EVB). The first patch drops the undocumented timer0 clock-names property. The second patch reorders timer0 and PECI so the APB child nodes stay in ascending unit-address order. The third patch introduces peripheral nodes for Ethernet, MMC, SPI, USB, RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device tree. The fourth patch cleans up the pre-existing NPCM845 EVB DTS property ordering to match strict dt-check-style expectations. The fifth patch enables the NPCM845-EVB peripherals, adding MDIO nodes, reserved memory, aliases, and board-specific configurations such as PHY modes and SPI flash partitions. The NPCM8XX device tree was tested on NPCM845 evaluation board. Addressed comments from: - Andrew Jeffery: https://lore.kernel.org/all/22ecb2fc6f4a4ca3c3018fffba8a56bcf5ca89fc.camel@codeconstruct.com.au/ Changes since version 9: - Modify dts code style. Changes since version 8: - Split the EVB changes into a DTS coding-style cleanup patch for the pre-existing board file and a separate peripheral enablement patch. - Fix strict dt-check-style issues in the EVB DTS by reordering properties and nodes, normalizing blank lines and continuation alignment, and lowercasing hex literals. - Drop the unused tip_reserved label. - Keep patches 1-3 unchanged. - The remaining refclk unused-label report is a false positive because the label is referenced from the included common DTSI. Changes since version 7: - Move timer0 to keep APB child nodes in unit-address order. - Add PSPI to the commit message. Changes since version 6: - Remove IPMI I2C device. - Add FIX enable property. - Keep patches 1-3 unchanged. Changes since version 5: - Add no-map to the tip_reserved firmware memory region. - Drop the unsupported snps,eee-force-disable property from gmac1. - Rework the FIU0 boot flash layout into nested fixed-partitions under the bmc container. - Keep patches 1-3 unchanged. Changes since version 4: - Split the timer0 clock-names cleanup into a separate first patch. - Remove nuvoton,sysgcr from udc8 and udc9. - Rename apb: bus@f0000000 back to apb. - Rename spix-mode to nuvoton,spix-mode. - Keep cooling-levels as 32-bit cells while encoding fan-tach-ch as /bits/ 8. Changes since version 3: - Remove tmp100. Changes since version 2: - Fix DTS warning. - Arrange node order by ascending unit address. Changes since version 1: - Fix commit message. - Fix dtbs_check warnings. Tomer Maimon (5): arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes arm64: dts: nuvoton: npcm845: Add peripheral nodes arm64: dts: nuvoton: npcm845-evb: Fix DTS coding style arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 721 +++++++++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 441 ++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 7 + 3 files changed, 1149 insertions(+), 20 deletions(-) -- 2.34.1