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Mon, 3 Aug 2026 12:40:54 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Sudip Mukherjee , Serge Semin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Changhuang Liang Subject: [PATCH v2 03/11] spi: dw: add check for support of enhanced spi Date: Mon, 3 Aug 2026 05:40:36 -0700 Message-Id: <20260803124044.156998-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803124044.156998-1-changhuang.liang@starfivetech.com> References: <20260803124044.156998-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::32) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: c8a19ada-5003-452a-aec2-08def15c758b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|23010399003|38350700014|6133799003|10067099003|56012099006|22082099003|18002099003|3023799007; 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Add the single/dual/quad/octal if the controller has the DW_SPI_CAP_EMODE capability. The DW_SPI_CAP_EMODE capability will be enabled in a later patch. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 34 +++++++++++++++++++++++++++++++++- drivers/spi/spi-dw.h | 1 + 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 7601a53d6f34..7275b7a9945f 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -518,6 +518,35 @@ static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op) return 0; } +static bool dw_spi_supports_enh_mem_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (op->addr.nbytes != 0 && op->addr.buswidth != 1 && + op->addr.buswidth != op->data.buswidth) + return false; + + if (op->addr.nbytes >= 8) + return false; + + if (op->cmd.buswidth != 1 && op->cmd.buswidth != op->addr.buswidth && + op->cmd.buswidth != op->data.buswidth) + return false; + + if (op->dummy.nbytes && !op->dummy.buswidth) + return false; + + if (op->dummy.nbytes != 0 && op->data.dir == SPI_MEM_DATA_OUT) + return false; + + /* WAIT_CYCLES is a 5-bit field in SPI_CTRLR0 */ + if (op->dummy.nbytes != 0 && + op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > + FIELD_MAX(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK)) + return false; + + return spi_mem_default_supports_op(mem, op); +} + static bool dw_spi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -800,7 +829,10 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws) if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && !dws->set_cs) { dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size; - dws->mem_ops.supports_op = dw_spi_supports_mem_op; + if (dws->caps & DW_SPI_CAP_EMODE) + dws->mem_ops.supports_op = dw_spi_supports_enh_mem_op; + else + dws->mem_ops.supports_op = dw_spi_supports_mem_op; dws->mem_ops.exec_op = dw_spi_exec_mem_op; if (!dws->max_mem_freq) dws->max_mem_freq = dws->max_freq; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 16a8c7ab7364..81a433ab759b 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -35,6 +35,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_DFS32 BIT(1) +#define DW_SPI_CAP_EMODE BIT(2) /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00 -- 2.25.1