From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E58147887F; Tue, 4 Aug 2026 16:39:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785861566; cv=none; b=VV+reSw5C/uCEubrqNVNSd3U46tu713jeEjJ8tWw1gD+fujcIaBToMPqm3JwJ8msRQKss36QeVhFg6xo1/pcotlilx6NoKjXyk2mT1NYttnOB8TDdN1QzJazuaa6MjfZIRxSCqP5rCDYvwcx/H3rHhR77Ew3HPy4iBT/UyFH6Cc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785861566; c=relaxed/simple; bh=VLx98O808QJ816QBW2ZJiP5s90c7VAO55fnojvHHlE8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MJ7XCqvU/Yhw6+kb4zofu3guixSH0TlMBuugLpMPV60wii2yTycHsy0nlqbiqzi+Mheda3YQbpy8JF7iYqgFnj6QmwolEbaFUzXk7n59ZkerY9t44Qbsl7NkNk4fYjGPFk7HZZkAbF1Siisl+WhVex9Oad99d1Hhi0dTW4phTns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=MxobwEN3; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="MxobwEN3" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 674Gc9qO51231946, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1785861490; bh=yPPKNOZubqToa6N7UffgfUQuz7B1uuXxaqbs4jamRMI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=MxobwEN3XnCx6w3CMG32e7inm6WRDMjzcSjIy8erdOc3dP5LxkMUd0V9NMjl7B4f2 CBEb5umHedO3sB21UhbLpjuiy/lgUsf8FkYazvVeKF+sF1BYzrrNuRj+H9mIMp5tSF jxQIKhl+9lRFwdUk2r/cUuxSVUgk7lEb0Md2V3mrq1G1AYpkNSkF4VSihVh+IM6dAy 1pNpbT0n8wuhk4SZcCyHjgu7seeoaIk2+ZubwoMxPsC2QJDDx3eI5U1VVNyz5L4AZe dUYRwC2AsH6KTyz6u7d49A/Am2h1lSFw/vIjYU/IsjsItyHHTtOUWfOfJGlkDG8SBp VsmH9Cj3qdE6Q== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 674Gc9qO51231946 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Aug 2026 00:38:09 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 5 Aug 2026 00:38:09 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 5 Aug 2026 00:38:09 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v12 06/11] clk: realtek: Add support for gate clock Date: Wed, 5 Aug 2026 00:38:02 +0800 Message-ID: <20260804163807.1285869-7-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260804163807.1285869-1-eleanor.lin@realtek.com> References: <20260804163807.1285869-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Cheng-Yu Lee Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and for standard regmap gate clocks. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Reviewed-by: Brian Masney Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v12: - Add Reviewed-by tag from Brian. - Change 'gate_ofs' type to 'unsigned int'. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-gate.c | 70 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 71edc18121c6..840aff067b61 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += clk-rtk-common.o clk-rtk-y += clk-pll.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c new file mode 100644 index 000000000000..1c32a87d97df --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +static int rtk_clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void rtk_clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = 0; + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int rtk_clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops = { + .enable = rtk_clk_regmap_gate_enable, + .disable = rtk_clk_regmap_gate_disable, + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "CLK_REALTEK"); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops = { + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "CLK_REALTEK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h new file mode 100644 index 000000000000..9303adda3166 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "clk-rtk-common.h" + +struct rtk_clk_regmap_gate { + struct rtk_clk_regmap clkr; + unsigned int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __rtk_clk_regmap_gate_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) + +#define __RTK_CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct rtk_clk_regmap_gate *to_rtk_clk_regmap_gate(struct clk_hw *hw) +{ + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); + + return container_of(clkr, struct rtk_clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ -- 2.43.0