From: Thierry Reding <thierry.reding@kernel.org>
To: "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Karthikeyan Mitran" <m.karthikeyan@mobiveil.co.in>,
"Hou Zhiqiang" <Zhiqiang.Hou@nxp.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Pali Rohár" <pali@kernel.org>,
"Michal Simek" <michal.simek@amd.com>,
"Kevin Xie" <kevin.xie@starfivetech.com>,
"Thierry Reding" <thierry.reding@kernel.org>,
"Aksh Garg" <a-garg7@ti.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Thierry Reding <treding@nvidia.com>
Subject: [PATCH v9 5/5] arm64: tegra: Add PCIe root ports on Tegra264
Date: Wed, 05 Aug 2026 13:57:24 +0200 [thread overview]
Message-ID: <20260805-tegra264-pcie-v9-5-fa2ed7350ae1@nvidia.com> (raw)
In-Reply-To: <20260805-tegra264-pcie-v9-0-fa2ed7350ae1@nvidia.com>
From: Thierry Reding <treding@nvidia.com>
The bindings have been updated to use the PCIe root port bindings, so
the nodes for the root ports must be added.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 66 +++++++++++++++++++++++++++++---
1 file changed, 60 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index cf9760c681b1..31bd29df8e46 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3562,10 +3562,19 @@ pci@c000000 {
ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
<0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x0 0xff>;
nvidia,bpmp = <&bpmp 0>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pinmux_main: pinmux@c281000 {
@@ -4015,10 +4024,19 @@ pci@8400000 {
ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */
<0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 1>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pci@8420000 {
@@ -4047,10 +4065,19 @@ pci@8420000 {
ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */
<0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 2>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pci@8440000 {
@@ -4079,10 +4106,19 @@ pci@8440000 {
ranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */
<0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 3>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pci@8460000 {
@@ -4111,10 +4147,19 @@ pci@8460000 {
ranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */
<0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 4>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pci@8480000 {
@@ -4143,10 +4188,19 @@ pci@8480000 {
ranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */
<0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */
<0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
- bus-range = <0x00 0xff>;
nvidia,bpmp = <&bpmp 5>;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.54.0
next prev parent reply other threads:[~2026-08-05 11:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-05 11:57 [PATCH v9 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-08-05 11:57 ` [PATCH v9 1/5] dt-bindings: pci: tegra264: Strictly distinguish C0 from C1-C5 Thierry Reding
2026-08-05 12:06 ` sashiko-bot
2026-08-05 11:57 ` [PATCH v9 2/5] dt-bindings: pci: tegra264: Switch to PCIe root port bindings Thierry Reding
2026-08-05 12:09 ` sashiko-bot
2026-08-05 15:12 ` Rob Herring (Arm)
2026-08-05 11:57 ` [PATCH v9 3/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-08-05 12:10 ` sashiko-bot
2026-08-05 15:51 ` Manivannan Sadhasivam
2026-08-05 11:57 ` [PATCH v9 4/5] arm64: tegra: Reorder reg and reg-names to match bindings Thierry Reding
2026-08-05 12:05 ` sashiko-bot
2026-08-05 11:57 ` Thierry Reding [this message]
2026-08-05 12:05 ` [PATCH v9 5/5] arm64: tegra: Add PCIe root ports on Tegra264 sashiko-bot
2026-08-05 15:55 ` Manivannan Sadhasivam
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