From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 400B640EBA1; Thu, 6 Aug 2026 08:48:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786006105; cv=none; b=flVmFPTzm4kNnVloYGZMT7fiR7LoQs0Sm6Tq5tsxcrehg98itEy4qdO9d2SL24EW9N6m/S02QSOCogYoLCCf3EpYbUFePqJKeEkjaNA3cG5h4SOAle82piriA3zjz/JRJosKJvhVyRrN6eCA1ZTWT/imuaWAf4sPlugdNCw0gLo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786006105; c=relaxed/simple; bh=Av6eeg2ekqj+HOs2zrQPFQA1RnGOcXg/+B9uTPlD7J8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gcvXPx/ZuKUgDB/QSes6b9duKWAcVRaWhOdsaqeREUEO84Uv7UJI6Xs7QVsGD7/ep7jc7rb3lrZnd5jvIdcdiqRlFGODTvPzV93tvb8OZUdUB4Guc3Y0ixoDoKpZNaU7pcPdXPdQWh9rs/a6r6gPZJgoqUhTzmOKvJ8IMaMIAhM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=yk28ZaYu; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="yk28ZaYu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1786006104; x=1817542104; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Av6eeg2ekqj+HOs2zrQPFQA1RnGOcXg/+B9uTPlD7J8=; b=yk28ZaYuELxWDDVmzkdYml8yg/pN9rjRtrYyMyb5sj7OWoWXTVmsUFZZ 8v2BKZcOnf78GpMWp9OnDIE/HddEJiUEjt+M+inkso4K8n+/7h3FugQxe 1borcNBSIMb94meF8uys8Yr1RMuvaqfUQqQIFSU+VR79y/h5118apQcUI HURrKRVCuQDkZFRAjcOgo3TJiv8SqV08axlypIXfZEJ8nDT4T+S4JYTSS h0s0mlEDBJGe28lJjF5hDoiwAS1cQ+sDFmD0hEzB9N3hYtb4x6JEbyLe1 z1RDv2dgtrvQQWabPBNReMycgOtMTTRv2NJ7SM/RVtp8j8lfEM4OmAzql g==; X-CSE-ConnectionGUID: yzc83y/kShyu5EyMOZukiw== X-CSE-MsgGUID: JFqw/C8BSrGRhFMPXS0v5w== X-IronPort-AV: E=Sophos;i="6.25,208,1779174000"; d="scan'208";a="60854115" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Aug 2026 01:48:23 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Thu, 6 Aug 2026 01:48:22 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 6 Aug 2026 01:48:14 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 10/17] nvmem: microchip-otpc: nvmem: add emulation mode and OTP access validation Date: Thu, 6 Aug 2026 13:10:17 +0530 Message-ID: <20260806074024.531259-11-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260806074024.531259-1-varshini.rajendran@microchip.com> References: <20260806074024.531259-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Add validation of OTP memory accessibility and emulation mode status during probe. When the boot packet is not configured, emulation mode allows access to the other packets. When both are not available an informational message is logged to help with debugging. Signed-off-by: Varshini Rajendran --- drivers/nvmem/microchip-otpc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index a17f82afdc37..6b0184423463 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -18,6 +18,7 @@ #define MCHP_OTPC_CR_READ BIT(6) #define MCHP_OTPC_MR (0x4) #define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_MR_EMUL BIT(7) #define MCHP_OTPC_AR (0x8) #define MCHP_OTPC_SR (0xc) #define MCHP_OTPC_SR_READ BIT(6) @@ -343,7 +344,8 @@ static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct mchp_otpc *otpc; - u32 size; + bool emul_enable; + u32 size, mr_val; int ret; otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); @@ -355,10 +357,22 @@ static int mchp_otpc_probe(struct platform_device *pdev) return PTR_ERR(otpc->base); otpc->dev = &pdev->dev; + + mr_val = readl_relaxed(otpc->base + MCHP_OTPC_MR); + emul_enable = mr_val & MCHP_OTPC_MR_EMUL; + if (emul_enable) + dev_info(otpc->dev, "Emulation mode enabled\n"); + ret = mchp_otpc_init_packets_list(otpc, &size); if (ret) return ret; + if (!size) { + dev_warn(otpc->dev, "Cannot access OTP memory\n"); + if (!emul_enable) + dev_info(otpc->dev, "Boot packet not programmed and emulation mode disabled\n"); + } + mchp_nvmem_config.dev = otpc->dev; mchp_nvmem_config.add_legacy_fixed_of_cells = true; mchp_nvmem_config.size = size; -- 2.34.1