Re: [PATCH v10 10/10] arm64: dts: qcom: eliza: Add support for MM clock controllers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device tree nodes for gpucc, videocc, and camcc are inserted out of unit-address sorting order.
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--- Patch [10]: [PATCH v10 10/10] arm64: dts: qcom: eliza: Add support for MM clock controllers ---
commit 1e9fc02b64bc332e46fe1a0e852faed44bcbabfb
Author: Taniya Das <taniya.das@oss.qualcomm.com>

arm64: dts: qcom: eliza: Add support for MM clock controllers

Add the device nodes for the multimedia clock controllers (cambistmclkcc,
camcc, videocc, gpucc) for Qualcomm Eliza SoC.

> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> index 66ea4aaafd73a..94297e05677ae 100644
> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
[ ... ]
> @@ -2893,6 +2914,60 @@ mdss_dp0_out: endpoint {
>  			};
>  		};
>  
> +		gpucc: clock-controller@3d90000 {

[Severity: Low]
Are the newly added nodes (gpucc@3d90000, videocc@aaf0000, camcc@ade0000)
inserted out of unit-address sorting order here?

They appear to be placed after the mdss@ae00000 node which has a higher unit
address. Does this violate the device tree convention requiring child nodes
to be sorted by unit address in ascending order?

> +			compatible = "qcom,eliza-gpucc";
> +			reg = <0x0 0x03d90000 0x0 0xa000>;
> +
> +			clocks = <&bi_tcxo_div2>,
> +				 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
> +
> +			power-domains = <&rpmhpd RPMHPD_MX>,
> +					<&rpmhpd RPMHPD_CX>;
> +			required-opps = <&rpmhpd_opp_low_svs>,
> +					<&rpmhpd_opp_low_svs>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806-eliza-mm-cc-v9-v10-0-6ba52dd14343@oss.qualcomm.com?part=10