Re: [PATCH v6 10/10] arm64: dts: renesas: r9a08g046l48-smarc: Add USB2.0 support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Port 0 is configured as OTG but uses host-only pinmux assignments, omitting the OTG_ID and VBUS detection pins.
- [High] The `hsusb` (USB 2.0 peripheral controller) is not enabled, which breaks the intended USB OTG (dual-role) functionality on Port 0.
--

--- Patch [10]: [PATCH v6 10/10] arm64: dts: renesas: r9a08g046l48-smarc: Add USB2.0 support ---
commit 1cbadfb3da8608db303bdf06f3c33654c1b1550b
Author: Biju Das <biju.das.jz@bp.renesas.com>

arm64: dts: renesas: r9a08g046l48-smarc: Add USB2.0 support
    
Enable USB2.0 on the RZ/G3L SMARC board (r9a08g046l48-smarc). Port 0
(ehci0, ohci0, usb2_phy0) is configured as OTG and Port 1 is configured
as host-only. The phyrst USB PHY reset controller is also enabled.

> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> @@ -71,6 +71,16 @@ codec_dai: codec {
>  #endif
>  };
>  
> +&ehci0 {
> +	dr_mode = "otg";
> +	status = "okay";
> +};

[Severity: High]
Port 0 is explicitly configured for OTG, which requires both a host
controller and a peripheral controller. However, the device tree for the
RZ/G3L SoC appears to lack the hsusb peripheral controller node.

If the PHY attempts to switch to peripheral mode when a device cable is
attached, will this silently fail to operate in device mode because there
is no USB gadget controller instantiated to handle the traffic?

[ ... ]

> @@ -181,6 +205,16 @@ ssi0_pins: ssi0 {
>  			 <RZG3L_PORT_PINMUX(H, 2, 9)>, /* SSIF0_RCK */
>  			 <RZG3L_PORT_PINMUX(H, 3, 9)>; /* SSIF0_TXD */
>  	};
> +
> +	usb0_pins: usb0 {
> +		pinmux = <RZG3L_PORT_PINMUX(3, 0, 12)>, /* USB20_OVRCUR */
> +			 <RZG3L_PORT_PINMUX(3, 1, 12)>; /* USB20_VBUSEN */
> +	};

[Severity: High]
This pinmux defines the OTG port configuration, but it seems to omit the
OTG_ID and VBUS detection pins. Since renesas,no-otg-pins is not
specified for usb2_phy0 later in the patch, the PHY driver expects
hardware role detection based on the ID pin.

Without the OTG_ID pin configured, can the physical PHY accurately detect
role changes? Could leaving this unconfigured cause the pin state to float,
preventing role switching entirely or causing spurious role changes that
break USB functionality?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806102236.149159-1-biju.das.jz@bp.renesas.com?part=10