Re: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Overlapping child address ranges in the `dma-ranges` property of `bus_nioc`.
- [Medium] Incorrect variant bitmask for PMU Event ID 34 in `riscv,raw-event-to-mhpmcounters`.
--

--- Patch [5]: [PATCH v3 5/5] riscv: dts: starfive: jhb100: Add JHB100 base DT ---
commit 6747fd56a0417ce034668e51d45ea97227861dc1
Author: Ley Foon Tan <leyfoon.tan@starfivetech.com>

riscv: dts: starfive: jhb100: Add JHB100 base DT

This commit adds the base device tree sources for the StarFive JHB100
SoC and the corresponding EVB-1 board. It introduces support for 4 
Dubhe-70 cores, along with basic peripherals including PMU, CLINT,
PLIC, and UART.

> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> new file mode 100644
> index 0000000000000..14ab83ed4482a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -0,0 +1,331 @@

[ ... ]

> +	pmu {
> +		compatible = "riscv,pmu";

[ ... ]

> +		riscv,raw-event-to-mhpmcounters =
> +			<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,	/* Event ID 1-31 */
> +			<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,	/* Event ID 32-33 */
> +			<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;	/* Event ID 34 */

[Severity: Medium]
Is the variant mask 0xFFFFFF22 correct for Event ID 34?

This mask appears to allow several bits (7, 6, 4, 3, 2, and 0) to vary,
which could cause other hardware PMU events to incorrectly match this rule
and route to the counters designated for Event 34.

> +	};

[ ... ]

> +		bus_nioc: bus {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-noncoherent;
> +			dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
> +				     <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;

[Severity: High]
Does this dma-ranges property incorrectly define overlapping child addresses?

Both entries define the exact same child DMA address space (<0x4 0x00000000>
with a size of <0x2 0x0>).

When parsed, standard OF translation matches the first entry, which entirely
shadows the second entry and could make its parent physical memory range
unreachable for DMA from this bus.

> +			ranges;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806122553.182449-1-changhuang.liang@starfivetech.com?part=5