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[79.42.255.151]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47ff79a7f07sm8070586f8f.8.2026.08.06.09.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:53:42 -0700 (PDT) From: Christian Marangi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock Date: Thu, 6 Aug 2026 18:53:30 +0200 Message-ID: <20260806165334.7328-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This small series introduce support for 2-lanes mode for Airoha AN7581 SoC. This is needed for correctly functionality of Eagle WiFi Card normally attached to this SoC that require a 2-line PCIe card to correctly work (and give the proper performance) The first 2 patch address a limitation of the PCIe implementation where the PERSTOUT reset were indirectly asserted and deasserted all at the same time (for all the 3 PCIe card) with PCIe enable and disable. The 2 patch address this and introduce correct reset to control reset line for the relevant PCIe line. The last 2 patch add additional logic and support to assert and deassert the PERSTOUT and also apply the required configuration for 2-lanes mode. 2-lanes mode is implemented in DT by adding the required property and by defining the "num-lanes" to 2. Changes v5: - Address formal comments from Bjorn - Drop clk patch (handled in separate series) - Add reference to clk changes Changes v4: - Improve DT split patch (drop unneeded property) - Handle power_down PERSTOUT Changes v3: - Add Ack from Krzysztof - Improve commit description of PCIe patch - Use pcie->num_lanes instead of possible uninit variable num_lanes Changes v2: - Address typo regs -> reg in Documentation - Address typo lan -> lane in Documentation - Apply a suggested fix from Airoha for PCIe MUX configuration before PHY init - Parse secondary reg in probe - Add missing reset_status handling for inverted bits - Move SCU to local handling in power_up - Add check for max num-lanes for EN7581 Christian Marangi (2): dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 .../bindings/pci/airoha,en7581-pcie.yaml | 244 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- drivers/pci/controller/pcie-mediatek-gen3.c | 106 ++++++-- 3 files changed, 338 insertions(+), 89 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml -- 2.53.0