From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-179.mta0.migadu.com (out-179.mta0.migadu.com [91.218.175.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CCB46EF66; Fri, 7 Aug 2026 08:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786090238; cv=none; b=MoKDkCyjUbXu6vJuFMqnINas/2T3MJad28UNveF0WtugFgvJYB/PVnRH7m0wxkoj3xJwtntSwDRgmIDHoe0qh8p19K2IHzz60vmBbFKmHISsx9VFNNr/G2jetl/Y7fCQyw7+UjhYZjcdI9JgNx73QA5zfc0AgFJY37KfNlfpJPI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786090238; c=relaxed/simple; bh=PziB6+6pLpNjee0JwACVhpsJ8rg/yPqjCJuzCsmMw6k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GbzlyypXbbzkNiiXnzJiXywIOJQ6B/Ba94u05hFqA3vmmnez14gODU1qrsw+RgPxeqeQb7hVM0JU9eM4JnpTNvfhgkWYmMiRC1GzOZ3uAOYuMMXKzCwb2eFXav+S26jn+r5ICBYTjDPncslG8zAcTpszYLMHiMGHGvxhzbHbJnw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=DV3cbjQI; arc=none smtp.client-ip=91.218.175.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="DV3cbjQI" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1786090231; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BfYXgw69zMSEclDnNr5kszfAFVsyyRX4EV9lqJDD4s4=; b=DV3cbjQIASZzTdDYM1EnEUE7GAYOSygcGnb5EH9Hra5RBZsKD8Nh5NASPHOZtCY1mMV/c5 6NhXvWxFUpwJ/KCsY+aOCZL+7z2UocgrY7QqgAMgIwaC6+rK1rRXXt6tMafdYFnxzntcSt yN6LOVxSRlvsIYXQWrCV8wyymzLXs3g= From: Atish Patra Date: Fri, 07 Aug 2026 01:09:12 -0700 Subject: [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260807-counter_delegation-v9-17-58658104e487@meta.com> References: <20260807-counter_delegation-v9-0-58658104e487@meta.com> In-Reply-To: <20260807-counter_delegation-v9-0-58658104e487@meta.com> To: Will Deacon , Atish Patra , Arnaldo Carvalho de Melo , Anup Patel , Ian Rogers , Rob Herring , Paul Walmsley , Mark Rutland , Jiri Olsa , Krzysztof Kozlowski , James Clark , Namhyung Kim Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Conor Dooley , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org X-Migadu-Flow: FLOW_OUT From: Atish Patra Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins --- drivers/perf/riscv_pmu_sbi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index ee0c07785927..5eb49db8bc7c 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -130,7 +130,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_group = { .attrs = riscv_cdeleg_pmu_formats_attr, }; +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=" RVPMU_EVENT_ATTR_RESOLVE(mask)) + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init = { + .name = "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] = { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -446,11 +459,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, \ + _cache_event_map, _attrs) \ { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ - .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ + .attrs_events = _attrs }, static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { }; @@ -472,6 +488,8 @@ static void __init rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid == arch_id) { current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + riscv_cdeleg_pmu_event_group.attrs = + pmu_vendor_events_table[i].attrs_events; break; } } -- 2.53.0-Meta