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From: sashiko-bot@kernel.org
To: "Atish Patra" <atish.patra@linux.dev>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org,
	linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs
Date: Fri, 07 Aug 2026 08:40:38 +0000	[thread overview]
Message-ID: <20260807084039.C31611F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260807-counter_delegation-v9-17-58658104e487@meta.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The macro RVPMU_EVENT_ATTR_RESOLVE performs single-level stringification, preventing macro expansion of event configuration values.
--

--- Patch [17]: [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs ---
commit b1ff3421691bcc5997cb4d931f9fdffb9eef0d1c
Author: Atish Patra <atishp@rivosinc.com>

RISC-V: perf: Add legacy event encodings via sysfs

This commit defines sysfs entries for legacy events to expose event
encoding and counter maps to tools like perf.

> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index ee0c077859273..5eb49db8bc7c1 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -130,7 +130,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_group = {
>  	.attrs = riscv_cdeleg_pmu_formats_attr,
>  };
>  
> +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m

[Severity: Medium]
Does this single-level stringification handle macro arguments correctly?

If a platform driver defines event mappings and passes standard kernel macros
for the config or mask arguments to RVPMU_EVENT_CMASK_ATTR, this definition
will stringify them verbatim without evaluation.

For example, passing a macro like RISCV_PMU_CYCLE_FIXED_CTR_MASK would emit
the literal string "event=RISCV_PMU_CYCLE_FIXED_CTR_MASK" instead of its
numeric value. This breaks the perf tool's ability to parse the event
encoding, rendering the PMU events unusable.

Would it be better to use __stringify() from linux/stringify.h so that both
literal numbers and macros evaluate correctly?

> +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \
> +	PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \
> +			      "event=" RVPMU_EVENT_ATTR_RESOLVE(config) \
> +			      ",counterid_mask=" RVPMU_EVENT_ATTR_RESOLVE(mask))
> +

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260807-counter_delegation-v9-0-58658104e487@meta.com?part=17

  reply	other threads:[~2026-08-07  8:40 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-07  8:08 [PATCH v9 00/20] Add Counter delegation ISA extension support Atish Patra
2026-08-07  8:08 ` [PATCH v9 01/20] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-08-07  8:30   ` sashiko-bot
2026-08-07  8:08 ` [PATCH v9 02/20] RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions Atish Patra
2026-08-07  8:08 ` [PATCH v9 03/20] RISC-V: Add Smcsrind and Sscsrind ISA extension definition and parsing Atish Patra
2026-08-07  8:08 ` [PATCH v9 04/20] dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions Atish Patra
2026-08-07  8:09 ` [PATCH v9 05/20] RISC-V: Define indirect CSR access helpers Atish Patra
2026-08-07  8:27   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 06/20] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-08-07  8:09 ` [PATCH v9 07/20] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-08-07  8:09 ` [PATCH v9 08/20] RISC-V: Add Ssccfg extension CSR definition Atish Patra
2026-08-07  8:09 ` [PATCH v9 09/20] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-08-07  8:25   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 10/20] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-08-07  8:09 ` [PATCH v9 11/20] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-08-07  8:09 ` [PATCH v9 12/20] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-08-07  8:29   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 13/20] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-08-07  8:09 ` [PATCH v9 14/20] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-08-07  8:34   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 15/20] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-08-07  8:09 ` [PATCH v9 16/20] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-08-07  8:43   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-08-07  8:40   ` sashiko-bot [this message]
2026-08-07  8:09 ` [PATCH v9 18/20] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-08-07  8:41   ` sashiko-bot
2026-08-07  8:09 ` [PATCH v9 19/20] tools/perf: Support event code for arch standard events Atish Patra
2026-08-07  8:09 ` [PATCH v9 20/20] tools/perf: Add RISC-V CounterIDMask event field Atish Patra

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