Re: [PATCH v9 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal

[sashiko-bot@kernel.org]

> Add support for the PCIe Root Port PERST# signal using the GPIO
> framework, along with the PCIe IP reset. This reset is managed
> by the driver and occurs after the Initial Power Up sequence
> (PCIe CEM r6.0, 2.2.1) is handled in hardware before the driver's
> probe function is called.
> 
> This is useful in warm reset scenarios where the power rails stay stable
> and only PERST# is toggled. Applying both the IP reset and PERST# resets
> the Root Port controller and Endpoint synchronously, improving
> reliability and avoiding lane errors.
> 
> Both the reset GPIO and the reset controller are optional to keep
> backward compatibility with existing DTBs. Also add a PCIE_T_PERST_US
> (100 us) macro in pci.h for the PERST# active time (PCIe CEM r6.0,
> sec 2.11.2, "T_PERST").
> 
> As part of this, update the interrupt controller node parsing to use
> of_get_child_by_name() instead of of_get_next_child(), since the PCIe
> host bridge node now has multiple children. This ensures the correct
> node is selected during initialization.
> 
> Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260807140205.1070367-1-sai.krishna.musham@amd.com?part=2