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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fMqk+ggPgg6hpoy/LQnpD12B/hGenxVVTQLsC8a/U8bxywhAezSkuksKZcJ0BJaCEwoB3p6kziIk6KU+RmUVxA9A5s0iWRn7CX7VaNFBFTci+PSlBrrdlPpkV1WcRCaVKDIyzyNGjAZmiUeXJuzSkeKmyVAzvuVzjTpr8mV52UnneD/aGFwTspRP+k92IBKgvKCdRsFrX+ad2QPhDYAf6Vj3qoveO218xfqTxBPwGC6UzgkeLFLy5a11/EL66yiEmulj2HzDZ9s7aU9j85gG18+xdmr50u6vDbkb5wnd0OCXJqJonqYW9lK//tzhjZikqlgPZtVdIcfjfpfu1MrDZVBkqd0Ft5lOBTqjOH9zlGVvhmvyGDRleZbtpchLK4tBUSCs0DMupvWgCL/SWo2TScIC6AUf5+CrcuAyy6GMnt/jig6PDO5UjJpMvvp8DwrJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2026 10:53:09.7100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9f70eb9-e376-4812-67db-08def53b3c5c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7227 The AMD CPM6 PCIe controller is based on the Synopsys DesignWare PCIe IP. Add "intr" to snps,dw-pcie.yaml vendor-specific reg-names for the per-controller interrupt register region used by CPM6. Update amd,versal2-mdb-host.yaml with separate register definitions: - MDB5: 4 regions (slcr, config, dbi, atu) - CPM6: 5 regions (slcr, config, dbi, atu, intr) Signed-off-by: Sai Krishna Musham --- Changes in v4: - None Changes in v3: - Update subject to match history. - Move allOf to the end, after required block. - Drop the CPM6 example. Changes in v2: - Update the CPM6 device tree binding and example. v1 https://lore.kernel.org/all/20260402180006.486229-2-sai.krishna.musham@amd.com/ v2 https://lore.kernel.org/all/20260728202044.1785986-2-sai.krishna.musham@amd.com/ v3 https://lore.kernel.org/all/20260803144412.713639-2-sai.krishna.musham@amd.com/ --- .../bindings/pci/amd,versal2-mdb-host.yaml | 45 ++++++++++++++++--- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 + 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 406c15e1dee1..672589066854 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -9,27 +9,30 @@ title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller maintainers: - Thippeswamy Havalige -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - - $ref: /schemas/pci/snps,dw-pcie.yaml# - properties: compatible: - const: amd,versal2-mdb-host + enum: + - amd,versal2-mdb-host + - amd,versal2-cpm6-host + - amd,versal2-cpm6-host1 reg: + minItems: 4 items: - description: MDB System Level Control and Status Register (SLCR) Base - description: configuration region - description: data bus interface - description: address translation unit register + - description: CPM6 PCIe error and event interrupt registers reg-names: + minItems: 4 items: - const: slcr - const: config - const: dbi - const: atu + - const: intr ranges: maxItems: 2 @@ -92,6 +95,38 @@ required: - "#interrupt-cells" - interrupt-controller +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: amd,versal2-mdb-host + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + minItems: 4 + maxItems: 4 + - if: + properties: + compatible: + contains: + enum: + - amd,versal2-cpm6-host + - amd,versal2-cpm6-host1 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + minItems: 5 + maxItems: 5 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index b3216141881c..21f86609ddb6 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -117,6 +117,8 @@ properties: enum: [ ecam ] - description: AMD MDB PCIe SLCR region const: slcr + - description: AMD CPM6 PCIe error and event interrupt registers + const: intr allOf: - contains: enum: [ dbi, ctrl ] -- 2.44.4