From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A4029D281; Sun, 9 Aug 2026 13:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786281322; cv=none; b=n8HaTjpFE6uXE0veK8tEXhSm24ALFHqzLpAdTAbP/8C4fqQhIRw93v6mEjoqsQFRk7qF4sUBRziY6u+N50TJg1AwxOl8IYhjOiIr4Ta6jw51T3GJxyxO523nKysjxxp39qLjpX6HnfS3Vk4Og13EtO8U360Oe5VCdkSxKjr4A1U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786281322; c=relaxed/simple; bh=nXtZ+nvKaPR4e0kxD9q85O5p2VolIkFyzikHh79h080=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EsPYGc3EBE9D59vWWUnGuS5/hTHjfxDoRM2lf5Dd9jrd5qrcrPquUwPk4iSZoAq5CWfcDFIAn22ehfdgVOiM3y12s0aoJhqSzMd2trDmuVkms0eAHwRy3ZINNXs73nt6xkjxe1NoWM9BkS0rJ45qwa//Igl53iZWrkORSZ2RWqU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qTdGEthN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qTdGEthN" Received: by smtp.kernel.org (Postfix) with ESMTPS id B175AC2BCFF; Sun, 9 Aug 2026 13:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786281320; bh=nXtZ+nvKaPR4e0kxD9q85O5p2VolIkFyzikHh79h080=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qTdGEthNlU8qe5IRz89KZmVGOEP0kg1eOi852bW8zlZGKYJV4iw45nfE5/WRRBJNq PL8xW9/1ffIT8zNLNdxmuCYjtjAlsmtGlq5n7Mq7gHwqGeccGPLIVt4nSRHnCkjS9p NgrsnWZ+HHfUDAUoS1pZUMutut2XZf6jhz7Qz8Dv/vRRaIL3PclGe8DSxZ/ldfiK6x 2xrUTlDUZ4EdJjhcFzOM54IlQcqCLDFT+A+mZTbP4OpdcowCsG6jtvFmTByH0U20Pt 73AJ+aMyu7nVwc35qBC4HPNXJc6FlewCJp8G9Ge1MGlGJZsis1qhfI0t0Ulkeq9EcD GW2wS78bZNTXQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CD0EC5AD4E; Sun, 9 Aug 2026 13:15:20 +0000 (UTC) From: Cody Kang via B4 Relay Date: Sun, 09 Aug 2026 21:14:15 +0800 Subject: [PATCH v2 06/17] clk: spacemit: k3: parent eDP/DP pixel clock to the PHY PLL Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260809-k3-display-v2-6-327d7910bf71@gmail.com> References: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> In-Reply-To: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yao Zi , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Guodong Xu Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786281298; l=1278; i=codykang.hk@gmail.com; s=codykang; h=from:subject:message-id; bh=D1thhdzY/CUbnE8bdXM4DECedWsXa83klc5ru7yhZ0s=; b=t5kel38scVDrqSR6I6QlaT5Kh7e5XdYnVTYNum0UHMpsnvDt0sw3pzA0Qg2TIlztsR6bFhv5A +h5NzE+El8zBKumOLKjq8GGpCGYDxmzBk3yE/RecsFcVIsFzRru/9Cl X-Developer-Key: i=codykang.hk@gmail.com; a=ed25519; pk=Osn6/cs9Su/mHHw4P19cmVc3v2FMQfiWahjsN0vEkuk= X-Endpoint-Received: by B4 Relay for codykang.hk@gmail.com/codykang with auth_id=895 X-Original-From: Cody Kang Reply-To: codykang.hk@gmail.com From: Cody Kang The APMU eDP/DP pixel-clock muxes were parented to a placeholder, because their real parents (the DP PHY PLLs) did not exist as clocks yet. They do now, so point each mux at its PLL and let the pixel clock reach the controller through the clock framework. Signed-off-by: Cody Kang --- v2: - no change --- drivers/clk/spacemit/ccu-k3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index cb0c4277f72a8..afbbbd797826d 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -937,13 +937,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, static const struct clk_parent_data edp0_pclk_parents[] = { CCU_PARENT_HW(lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp0_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); static const struct clk_parent_data edp1_pclk_parents[] = { CCU_PARENT_HW(dsi4ln2_lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp1_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); -- 2.43.0