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([81.56.18.151]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4995c7b2b68sm209832495e9.4.2026.08.09.09.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 09:07:02 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 0/8] Properly describe mt6589 and mt8167 toprgu resets Date: Sun, 9 Aug 2026 18:03:24 +0200 Message-ID: <20260809160643.33991-1-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently mt8167 inherits its watchdog from the included mt8516 dtsi, which in turn falls back on mt6589-wdt, which does not support toprgu resets yet. This series adds support for mt6589 toprgu resets with bit definitions obtained from Android stock sources. However, according to its data sheet, mt8167 has 15 sw resets instead of 12, and its reset bits point to different subsystems than the mt6589 ones. If the number of resets varies between SoCs, the watchdog driver becomes incompatible. Therefore in the first three patches we improve the description of the, resets for mt6589 using the definitions obtained from Android sources. Then we introduce a dedicated mediatek,mt8167-wdt compatible for the watchdog driver that describes correctly this SoC's resets. Also while we're touching the bindings reset header, we add constants for the MMSYS resets. In the 7th patch we add a node for the mt8167 watchdog referring to the new compatible in the SoC dtsi. In the last patch, we define the mmsys reset table for the SoC. According to the datasheet, there are 28 mmsys reset bits divided across two adjacent registers. Changes in v3 [3]: - Improved explanations in the commit messages; - Added the #reset-cells property to mt6589 watchdog node; - Included the mediatek,mt6589-resets.h file in mt6589.dtsi; - Included the mediatek,mt8167-resets.h file in mt8167.dtsi; - Moved the mmsys reset table from the mt8167-mmsys.h header file to the mmsys driver implementation. Changes in v2 [2]: - Sashiko pointed out correctly a missing entry in the mmsys reset table in the last patch. Initial version: [1] [1] https://lore.kernel.org/linux-mediatek/20260717151134.678839-1-l.scorcia@gmail.com/ [2] https://lore.kernel.org/linux-mediatek/20260717163959.714561-1-l.scorcia@gmail.com/ Luca Leonardo Scorcia (8): dt-bindings: reset: Add mt6589 toprgu reset IDs watchdog: mediatek: Add wdt/toprgu resets for MT6589 arm: dts: mediatek: mt6589: Enable toprgu reset controller dt-bindings: watchdog: Add compatible for MediaTek mt8167 dt-bindings: reset: Add reset controller constants for mt8167 watchdog: mediatek: Add support for mt8167 TOPRGU/WDT arm64: dts: mt8167: Properly describe the SoC watchdog soc: mediatek: mtk-mmsys: Add resets for mt8167 .../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 + arch/arm64/boot/dts/mediatek/mt8167.dtsi | 8 +++ drivers/soc/mediatek/mt8167-mmsys.h | 3 ++ drivers/soc/mediatek/mtk-mmsys.c | 38 +++++++++++++ drivers/watchdog/mtk_wdt.c | 13 ++++- .../reset/mediatek,mt6589-resets.h | 24 +++++++++ .../reset/mediatek,mt8167-resets.h | 53 +++++++++++++++++++ 8 files changed, 141 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/reset/mediatek,mt6589-resets.h create mode 100644 include/dt-bindings/reset/mediatek,mt8167-resets.h -- 2.43.0