Re: [PATCH v4 1/2] dt-bindings: Add GPIO-locked fixed clock

[Conor Dooley <conor@kernel.org>]

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On Mon, Aug 10, 2026 at 11:54:03AM -0500, Rob Herring wrote:
> On Mon, Aug 10, 2026 at 11:40:00AM -0500, Rob Herring wrote:
> > On Sun, Jul 26, 2026 at 05:40:24PM +0000, Vyacheslav Yurkov wrote:
> > > Some hardware designs provide fixed-frequency clocks generated outside
> > > software control, such as by FPGA-resident PLLs. While the clock rate is
> > > fixed, a separate GPIO signal indicates whether the clock source is
> > > locked and producing a valid output.
> > > 
> > > Describe a GPIO-locked fixed clock provider that exposes a fixed-rate
> > > clock whose availability depends on one or more GPIO lock-status
> > > signals.
> > > 
> > > Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
> > 
> > I think you can drop this. Just update your author email.
> > 
> > > Signed-off-by: Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>
> > > ---
> > >  .../bindings/clock/gpio-locked-fixed-clock.yaml    | 59 ++++++++++++++++++++++
> > >  1 file changed, 59 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml b/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml
> > > new file mode 100644
> > > index 000000000000..4d17889c51ad
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/gpio-locked-fixed-clock.yaml
> > > @@ -0,0 +1,59 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/clock/gpio-locked-fixed-clock.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: GPIO Locked Fixed Clock
> > > +
> > > +maintainers:
> > > +  - Vyacheslav Yurkov <V.Yurkov.EXT@bruker.com>
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: gpio-locked-fixed-clock
> > > +
> > > +  "#clock-cells":
> > > +    const: 0
> > > +
> > > +  clocks:
> > > +    description: Input clocks whose validity is monitored by this provider.
> > > +
> > > +  clock-output-names:
> > > +    description: Names of the clock provided by this controller.
> > > +    maxItems: 1
> > > +
> > > +  locked-gpios:
> > > +    description: |
> > 
> > Don't need '|' if no formatting.
> > 
> > > +      GPIOs to check the lock state.
> > > +    minItems: 1
> > > +    maxItems: 32
> > 
> > Please explain better how multiple GPIOs work? Why would you ever have 
> > more than 1 lock signal per clock? And you can only have 1 clock given 
> > #clock-cells==0.
> > 
> > Do you have an immediate need for more than 1? If not, I'd drop 
> > support for it for now.
> 
> I missed that this is N input clocks and 1 output clock. But that leads 
> to other questions. You've implemented a clock mux then? I still don't 
> understand for what h/w that makes sense. Which input clock is selected? 
> The locked one?

Yeah, I thought this was n inputs and n outputs, with each gpio
signalling that an individual PLL had locked.

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