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Mon, 10 Aug 2026 06:37:26 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v5 21/21] riscv: dts: starfive: jhb100: Add pinctrl nodes Date: Sun, 9 Aug 2026 23:36:50 -0700 Message-Id: <20260810063650.239303-22-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260810063650.239303-1-changhuang.liang@starfivetech.com> References: <20260810063650.239303-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BJSPR01CA0019.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::31) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1284:EE_ X-MS-Office365-Filtering-Correlation-Id: dd6f6386-5315-472b-978e-08def6a9d7a9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|376014|7416014|52116014|10067099003|56012099006|22082099003|18002099003|38350700014|921020; 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They contain pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/ pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2. Simultaneously add the pinctrl reference for uart6. Co-developed-by: Lianfeng Ouyang Signed-off-by: Lianfeng Ouyang Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 3 + .../boot/dts/starfive/jhb100-pinctrl.dtsi | 23 ++++ arch/riscv/boot/dts/starfive/jhb100.dtsi | 110 ++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts index 462b6fb7953b..8ad2b30a4e0b 100644 --- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts @@ -4,6 +4,7 @@ */ #include "jhb100.dtsi" +#include "jhb100-pinctrl.dtsi" / { model = "StarFive JHB100 EVB-1"; @@ -29,4 +30,6 @@ memory@40000000 { &uart6 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins>; }; diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi new file mode 100644 index 000000000000..13d9ff146743 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2025-2026 StarFive Technology Co., Ltd. + */ + +#include + +&pinctrl_sys2 { + uart6_pins: uart6-grp { + uart6-tx-pins { + pins = ; + function = "uart"; + power-source = <3300>; + }; + + uart6-rx-pins { + pins = ; + function = "uart"; + input-enable; + power-source = <3300>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi index 943324b3b2fd..f9a7fa9d37e3 100644 --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -428,6 +428,19 @@ per0crg: clock-controller@11a08000 { #reset-cells = <1>; }; + pinctrl_per0: pinctrl@11a0a000 { + compatible = "starfive,jhb100-per0-pinctrl"; + reg = <0x0 0x11a0a000 0x0 0x1000>; + resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>; + interrupts = <60>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per0 0 0 0 32>, + <&pinctrl_per0 1 0 32 28>; + }; + per1crg: clock-controller@11b40000 { compatible = "starfive,jhb100-per1crg"; reg = <0x0 0x11b40000 0x0 0x1000>; @@ -443,6 +456,19 @@ per1crg: clock-controller@11b40000 { #reset-cells = <1>; }; + pinctrl_per1: pinctrl@11b42000 { + compatible = "starfive,jhb100-per1-pinctrl"; + reg = <0x0 0x11b42000 0x0 0x800>; + resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>; + interrupts = <61>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per1 0 0 0 32>, + <&pinctrl_per1 1 0 32 4>; + }; + per2crg: clock-controller@11bc0000 { compatible = "starfive,jhb100-per2crg"; reg = <0x0 0x11bc0000 0x0 0x1000>; @@ -464,6 +490,30 @@ per2crg: clock-controller@11bc0000 { #reset-cells = <1>; }; + pinctrl_per2: pinctrl@11bc2000 { + compatible = "starfive,jhb100-per2-pinctrl"; + reg = <0x0 0x11bc2000 0x0 0x400>; + resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>; + interrupts = <62>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per2 0 0 0 31>; + }; + + pinctrl_per2pok: pinctrl@11bc2400 { + compatible = "starfive,jhb100-per2pok-pinctrl"; + reg = <0x0 0x11bc2400 0x0 0x400>; + resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>; + interrupts = <63>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per2pok 0 0 0 18>; + }; + per3crg: clock-controller@11c40000 { compatible = "starfive,jhb100-per3crg"; reg = <0x0 0x11c40000 0x0 0x1000>; @@ -483,6 +533,18 @@ per3crg: clock-controller@11c40000 { #reset-cells = <1>; }; + pinctrl_per3: pinctrl@11c42000 { + compatible = "starfive,jhb100-per3-pinctrl"; + reg = <0x0 0x11c42000 0x0 0x1000>; + resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>; + interrupts = <64>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per3 0 0 0 11>; + }; + sys0crg: clock-controller@13000000 { compatible = "starfive,jhb100-sys0crg"; reg = <0x0 0x13000000 0x0 0x4000>; @@ -517,6 +579,54 @@ sys2crg: clock-controller@13008000 { #reset-cells = <1>; }; + pinctrl_sys0: pinctrl@13080000 { + compatible = "starfive,jhb100-sys0-pinctrl"; + reg = <0x0 0x13080000 0x0 0x800>; + resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>; + interrupts = <56>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys0 0 0 0 4>; + }; + + pinctrl_sys0h: pinctrl@13080800 { + compatible = "starfive,jhb100-sys0h-pinctrl"; + reg = <0x0 0x13080800 0x0 0x800>; + resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>; + interrupts = <57>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys0h 0 0 0 12>; + }; + + pinctrl_sys1: pinctrl@13081000 { + compatible = "starfive,jhb100-sys1-pinctrl"; + reg = <0x0 0x13081000 0x0 0x1000>; + resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>; + interrupts = <58>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys1 0 0 0 8>; + }; + + pinctrl_sys2: pinctrl@13082000 { + compatible = "starfive,jhb100-sys2-pinctrl"; + reg = <0x0 0x13082000 0x0 0x1000>; + interrupts = <59>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys2 0 0 0 32>, + <&pinctrl_sys2 1 0 32 5>; + }; + intc: interrupt-controller@13220000 { compatible = "starfive,jhb100-intc"; reg = <0x0 0x13220000 0x0 0x80>; -- 2.25.1