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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by SJ1PEPF00001CE8.mail.protection.outlook.com (10.167.242.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.6 via Frontend Transport; Mon, 10 Aug 2026 10:11:16 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Mon, 10 Aug 2026 05:10:59 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Mon, 10 Aug 2026 05:05:20 -0500 Received: from xhdappanad40.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.45 via Frontend Transport; Mon, 10 Aug 2026 05:05:16 -0500 From: Golla Nagendra To: , , , , , , CC: , , , , , , Subject: [PATCH V3 6/6] dmaengine: zynqmp_dma: Add per-channel reset support Date: Mon, 10 Aug 2026 15:34:52 +0530 Message-ID: <20260810100452.426320-7-nagendra.golla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260810100452.426320-1-nagendra.golla@amd.com> References: <20260810100452.426320-1-nagendra.golla@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|MW4PR12MB6753:EE_ X-MS-Office365-Filtering-Correlation-Id: 88716c31-c584-4f97-22b1-08def6c7b76b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|23010399003|82310400026|36860700016|6133799003|11063799006|56012099006|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PolPHrNw5Ibvhz6H2+S9JY64fV5zacPSRY2S9iY3wqyIvUPX50o6vSFbPDea5lZCM7d7w5XNcFVMl782dqpznS8aMmxPEgaXW7fI+xyity3+wi4JiU7UyXb3tFmoi14mzNxpjjcy+KD7WOokDp9crrBEEfgGY3cAE9PzGs7lp3Wvp13GKLV+YGQ9O5fLJkDzccKqIfD3j9mwuMZTVnGcxR6qc2tUr1iNuxz8ueyjF+R3R8uxtBPTm5Ci8j2k2/IMzfrs7rqsRuJEW0ORUC8mJTYU9Ibk0ChSbcZGzU+n0G3yna6Sd1v89GpSIQX3OkfK0UXU8oCAq2+3AQH+JMVWHPVuKy8RuutVSgrNJrfFhLiA4+IZHSyP5F61Nx/DuqFgW6jue42EbTHK4/IN/5dTblnOjUJP0CUdW4d0UhVNriebmTxy2bz7nuG7Z/yYd1g0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2026 10:11:16.7932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88716c31-c584-4f97-22b1-08def6c7b76b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6753 Versal Gen2 and Versal Net expose a dedicated reset line per ZDMA channel. Use device_reset() to trigger a mandatory reset pulse on the channel during probe when match data indicates reset is supported. The has_reset field in zynqmp_dma_config controls whether reset is performed for a given compatible. For Versal Net and Versal Gen2, has_reset is set to true, so device_reset() is called and probe fails if the resets property is missing in the device tree. For legacy SoCs, match_data is NULL and has_reset defaults to false,so the reset path is skipped entirely. Signed-off-by: Golla Nagendra --- Changes in V3: - Introduce has_reset flag in zynqmp_dma_config to gate the reset path per-compatible instead of calling device_reset() unconditionally - Move the of_device_get_match_data() call before the reset block so has_reset can be checked in the same code path that reads irq_offset --- drivers/dma/xilinx/zynqmp_dma.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index 7561416b8e62..7ec6598ea587 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../dmaengine.h" @@ -928,6 +929,14 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, if (IS_ERR(chan->regs)) return PTR_ERR(chan->regs); + match_data = of_device_get_match_data(&pdev->dev); + if (match_data && match_data->has_reset) { + err = device_reset(&pdev->dev); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to reset channel\n"); + } + chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64; chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN; chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN; @@ -943,7 +952,6 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, return -EINVAL; } - match_data = of_device_get_match_data(&pdev->dev); if (match_data) chan->irq_offset = match_data->offset; -- 2.43.7