Re: [PATCH v10 RESEND 1/6] arm64: dts: qcom: Add device tree for Nord SoC series

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing `cpu-idle-states` property in CPU nodes and incorrect use of `domain-idle-states` in CPU power domains.
- [High] All secondary high-temperature thermal trip points are incorrectly configured as `type = "passive"` instead of `type = "critical"`.
--

--- Patch [1]: [PATCH v10 RESEND 1/6] arm64: dts: qcom: Add device tree for Nord SoC series ---
commit 6e2b5a047ad42d9b919ebd0fbf1f8ae98bae9bab
Author: Shawn Guo <shengchao.guo@oss.qualcomm.com>
arm64: dts: qcom: Add device tree for Nord SoC series

This commit adds the base device tree include for the Qualcomm Nord SoC
series. It describes core components including 18 Oryon CPU cores,
GICv3, TLMM, thermal sensors, SMMU, QUPv3, SCMI, watchdog, and timers.

> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -0,0 +1,4623 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or subsidiaries.
> + */
> +
[ ... ]
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,oryon-1-5";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			power-domains = <&cpu0_pd>;
> +			power-domain-names = "psci";
> +			next-level-cache = <&l2_0>;
> +			clocks = <&cpu_perf 0>;
> +			#cooling-cells = <2>;

[Severity: High]
Should this CPU node (and the other CPU nodes) include the cpu-idle-states
property? Without it, the cpuidle framework may not discover and register
the CPU idle states, which could prevent the cores from entering deep idle
states and lead to excessive power consumption.

> +
> +			l2_0: l2-cache {
[ ... ]
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +
> +		cpu0_pd: power-domain-cpu0 {
> +			#power-domain-cells = <0>;
> +			power-domains = <&cluster0_pd>;
> +			domain-idle-states = <&core_off_c4>;
                        ^^^^^^^^^^^^^^^^^^

[Severity: High]
Does passing an arm,idle-state node here violate the DT schema? It appears
that domain-idle-states expects a genpd domain-idle-state cluster state,
rather than a CPU idle state.

> +		};
[ ... ]
> +	thermal_zones: thermal-zones {
> +		ddr-0-0-thermal {
> +			polling-delay-passive = <0>;
> +			polling-delay = <0>;
> +			thermal-sensors = <&tsens0 0>;
> +
> +			trips {
> +				trip-point0 {
> +					temperature = <105000>;
> +					hysteresis = <10000>;
> +					type = "passive";
> +				};
> +
> +				trip-point1 {
> +					temperature = <115000>;
> +					hysteresis = <10000>;
> +					type = "passive";
                                        ^^^^

[Severity: High]
Should this extreme temperature trip point be marked as "critical" instead
of "passive"?

If the SoC reaches 115C or 125C, a passive trip point will only instruct
the thermal framework to throttle via cooling devices. It won't trigger an
emergency shutdown, which might leave the hardware vulnerable to physical
damage from overheating. Is this pattern intentional across all the
thermal zones defined in this file?

> +				};
> +			};
> +		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260810114313.776563-1-shengchao.guo@oss.qualcomm.com?part=1