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On enable: reprogramme the DLL from the per-CS calibration result when the hardware values differ (handles alternating PHY reads across two chip selects with different calibration), configure read-capture for the tuned delay, assert PHY_EN and PHY_PIPELINE in CONFIG, and decrement the dummy cycle count by one since the PHY data-capture pipeline absorbs that latency. The original count is saved in cqspi->phy_saved_dummy so the disable path restores it exactly, handling the case where the original count was zero. On disable, all settings are reversed using the saved count. Add cqspi_use_tuned_phy() predicate: PHY is activated only when calibration completed successfully and the op frequency equals the post-config rate. For direct reads, PHY is used only when both the start address and end address are 16-byte aligned. Unaligned transfers fall back to non-PHY DMA. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 119 +++++++++++++++++++++++++++++- 1 file changed, 118 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 99a0ec0e769c..8903b4cf4f6f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1074,6 +1074,102 @@ static int cqspi_resync_dll(struct cqspi_st *cqspi) return ret; } +static int cqspi_tune_phy(struct cqspi_flash_pdata *f_pdata, bool enable) +{ + struct cqspi_st *cqspi = f_pdata->cqspi; + void __iomem *reg_base = cqspi->iobase; + u32 reg; + u8 dummy; + int ret; + + ret = cqspi_wait_idle(cqspi); + if (ret) + return ret; + + if (enable) { + /* + * CQSPI_REG_PHY_CONFIG holds the RX/TX delay line tap counts + * and is a single global register with no per-CS equivalent. + * Reprogramme and resync the DLL when the active device's + * calibrated values differ from what is currently in hardware, + * which happens when alternating PHY reads between two chip + * selects with different calibration results. + */ + reg = readl(reg_base + CQSPI_REG_PHY_CONFIG); + if (((reg >> CQSPI_REG_PHY_CONFIG_RX_DEL_LSB) & + CQSPI_REG_PHY_CONFIG_RX_DEL_MASK) != f_pdata->phy_setting.rx || + ((reg >> CQSPI_REG_PHY_CONFIG_TX_DEL_LSB) & + CQSPI_REG_PHY_CONFIG_TX_DEL_MASK) != f_pdata->phy_setting.tx) { + cqspi_set_dll(reg_base, f_pdata->phy_setting.rx, + f_pdata->phy_setting.tx); + ret = cqspi_resync_dll(cqspi); + if (ret) + return ret; + } + + cqspi_readdata_capture(cqspi, !f_pdata->use_dqs, f_pdata->use_dqs, + f_pdata->phy_setting.read_delay); + + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_PHY_EN | CQSPI_REG_CONFIG_PHY_PIPELINE; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + /* + * The PHY data-capture pipeline absorbs one dummy cycle's + * worth of latency; reduce the count to avoid over-compensation. + * Save the original count so the disable path can restore it + * exactly, regardless of whether the original was zero. + */ + reg = readl(reg_base + CQSPI_REG_RD_INSTR); + dummy = FIELD_GET(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + reg); + cqspi->phy_saved_dummy = dummy; + if (dummy) + dummy--; + reg &= ~(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |= FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + + ret = cqspi_wait_idle(cqspi); + if (ret) { + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(CQSPI_REG_CONFIG_PHY_EN | + CQSPI_REG_CONFIG_PHY_PIPELINE); + writel(reg, reg_base + CQSPI_REG_CONFIG); + reg = readl(reg_base + CQSPI_REG_RD_INSTR); + reg &= ~(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |= FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + cqspi->phy_saved_dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + } + return ret; + } + + cqspi_readdata_capture(cqspi, !cqspi->rclk_en, false, + f_pdata->read_delay); + + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(CQSPI_REG_CONFIG_PHY_EN | + CQSPI_REG_CONFIG_PHY_PIPELINE); + writel(reg, reg_base + CQSPI_REG_CONFIG); + + reg = readl(reg_base + CQSPI_REG_RD_INSTR); + reg &= ~(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |= FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + cqspi->phy_saved_dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + + return cqspi_wait_idle(cqspi); +} + static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx) @@ -1524,6 +1620,14 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, return cqspi_indirect_write_execute(f_pdata, to, buf, len); } +static bool cqspi_use_tuned_phy(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op, + u32 post_config_max_speed_hz) +{ + return f_pdata->use_tuned_phy && + op->max_freq == post_config_max_speed_hz; +} + static void cqspi_rx_dma_callback(void *param) { struct cqspi_st *cqspi = param; @@ -1629,6 +1733,7 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, loff_t from = op->addr.val; size_t len = op->data.nbytes; u_char *buf = op->data.buf.in; + int ret; if (!cqspi->rx_chan || !virt_addr_valid(buf) || len < CQSPI_PHY_MIN_DIRECT_READ_LEN) { @@ -1636,7 +1741,19 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, return 0; } - return cqspi_direct_read_dma(f_pdata, buf, from, len); + if (!cqspi_use_tuned_phy(f_pdata, op, post_config_max_speed_hz)) + return cqspi_direct_read_dma(f_pdata, buf, from, len); + + if (!IS_ALIGNED(from, 16) || !IS_ALIGNED(from + len, 16)) + return cqspi_direct_read_dma(f_pdata, buf, from, len); + + ret = cqspi_tune_phy(f_pdata, true); + if (ret) + return ret; + ret = cqspi_direct_read_dma(f_pdata, buf, from, len); + cqspi_tune_phy(f_pdata, false); + + return ret; } static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, -- 2.34.1