Re: [PATCH 3/3] power: supply: qcom_smbx: program AICL rerun time

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The watchdog interrupt handler writes to a register without adding the peripheral base address.
--

--- Patch [3]: [PATCH 3/3] power: supply: qcom_smbx: program AICL rerun time ---
commit 7ed13fc0edf8d350c9eda801c5d3ae1f45ee12b6
Author: Casey Connolly <casey.connolly@linaro.org>

power: supply: qcom_smbx: program AICL rerun time

The bootloader-provided automatic input current limit rerun interval is
not a stable software interface. Program a consistent three-second
interval during probe. This is required at least on SMB5 hardware.

> diff --git a/drivers/power/supply/qcom_smbx.c b/drivers/power/supply/qcom_smbx.c
> index 09d9e0f95cb56..9e3e240b68130 100644
> --- a/drivers/power/supply/qcom_smbx.c
> +++ b/drivers/power/supply/qcom_smbx.c
[ ... ]
> @@ -1384,6 +1385,14 @@ static int smb_probe(struct platform_device *pdev)
>  
>  	platform_set_drvdata(pdev, chip);
>  
> +	rc = regmap_write_bits(chip->regmap,
> +			       chip->base + AICL_RERUN_TIME_CFG,

[Severity: High]
This is a pre-existing issue, but seeing the correct usage of chip->base
here, is the regmap write in smb_handle_wdog_bark() writing to an arbitrary
PMIC peripheral?

drivers/power/supply/qcom_smbx.c:smb_handle_wdog_bark() {
	...
	rc = regmap_write(chip->regmap, BARK_BITE_WDOG_PET,
			  BARK_BITE_WDOG_PET_BIT);
	...
}

It appears to be missing chip->base, which could fail to pet the charger
watchdog and corrupt the state of another peripheral when the watchdog bark
interrupt fires.

> +			       AICL_RERUN_TIME_MASK,
> +			       AICL_RERUN_TIME_3_SECS);
> +	if (rc < 0)
> +		return dev_err_probe(chip->dev, rc,
> +				     "could not set AICL rerun time\n");
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260811-submit-qcom-smbx-send-v1-v1-0-feec6cfa123a@snyders.xyz?part=3