Re: [PATCH v4 1/6] dt-bindings: iio: accel: mma8452: Add drive-open-drain

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incomplete Implementation: The `drive-open-drain` property is added to the Device Tree bindings, but the corresponding driver implementation to actually configure the hardware is entirely missing.
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--- Patch [1]: [PATCH v4 1/6] dt-bindings: iio: accel: mma8452: Add drive-open-drain ---
commit 43db06f651ed5305e7ec90f57f0128f294c32c55
Author: Esben Haabendal <esben@geanix.com>

dt-bindings: iio: accel: mma8452: Add drive-open-drain

This commit adds a new drive-open-drain boolean property to the MMA8452
device tree binding. This allows configuring the interrupt pin to open drain
mode instead of the default push-pull mode.

> diff --git a/Documentation/devicetree/bindings/iio/accel/fsl,mma8452.yaml b/Documentation/devicetree/bindings/iio/accel/fsl,mma8452.yaml
> index b0dd2b4e116ab..20701aa725d07 100644
> --- a/Documentation/devicetree/bindings/iio/accel/fsl,mma8452.yaml
> +++ b/Documentation/devicetree/bindings/iio/accel/fsl,mma8452.yaml
> @@ -39,6 +39,12 @@ properties:
>      minItems: 1
>      maxItems: 2
>  
> +  drive-open-drain:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: the interrupt line will be configured as open drain, which is
> +      useful if several sensors share the same interrupt line. (This binding is
> +      taken from pinctrl.)

[Severity: High]
Is the corresponding driver implementation to actually configure the hardware
missing?

If a system integrator relies on this new property and physically wires
multiple sensor interrupts together, the missing driver implementation means
the sensors will silently remain in push-pull mode.

Looking at mma8452_probe() in drivers/iio/accel/mma8452.c, there appears
to be no logic to read drive-open-drain via device_property_read_bool()
and configure the sensor's CTRL_REG3 register (0x2C) accordingly.

If two push-pull outputs on a shared line drive different logic levels
simultaneously, can this create a short circuit that physically damages the
board?

> +
>    vdd-supply: true
>    vddio-supply: true

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Sashiko AI review · https://sashiko.dev/#/patchset/20260812-mma8452-open-drain-v4-0-bfca15d02b59@geanix.com?part=1