Re: [PATCH v6 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] RVA23U64 detection relies on the non-standard `RISCV_ISA_EXT_B` pseudo-extension instead of the mandated `Zba`, `Zbb`, and `Zbs` sub-extensions, causing conformant hardware to fail detection.
--

--- Patch [9]: [PATCH v6 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection ---
commit 96d9cbf0b8923400be62f448ef68daf8ad09dfb6
Author: Guodong Xu <guodong.xu@oss.qualcomm.com>

riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection

This commit introduces a per-hart and host-wide bitmap for ISA bases, such
as IMA and RVA23U64, computed during subsystem init. It provides a cached
detection mechanism to ensure system-wide consistency for subsequent
consumers like hwprobe and /proc/cpuinfo.

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index de7cff5f48c34..2ad8a16a0eff3 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c

[ ... ]

> @@ -1334,3 +1337,90 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> +static void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
> +{
> +	const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
> +	DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };

[ ... ]

> +	/* RVA23U64 */
> +
> +	/* Supm with PMLEN=7 */
> +	if (!riscv_have_user_pmlen(7))
> +		return;
> +
> +	__set_bit(RISCV_ISA_EXT_F, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_D, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_C, ext_mask);
> +	__set_bit(RISCV_ISA_EXT_B, ext_mask);

[Severity: High]
Does this cause conformant hardware to fail detection?

The RVA23U64 profile mandates the individual bit-manipulation extensions
Zba, Zbb, and Zbs. If a device tree explicitly lists these standard
extensions in riscv,isa-extensions without the unratified B pseudo-extension,
the device tree parser will set the individual extension bits but not
RISCV_ISA_EXT_B.

Since this mandate mask checks for the B pseudo-extension, bitmap_subset()
will fail for conformant hardware, breaking any system or userspace behavior
relying on this hwprobe base detection.

Should this check for RISCV_ISA_EXT_ZBA, RISCV_ISA_EXT_ZBB, and
RISCV_ISA_EXT_ZBS instead?

> +	__set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260812-rva23u64-hwprobe-v2-v6-0-c985af3256b8@oss.qualcomm.com?part=9