From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84A3E1A5B8C; Fri, 14 Aug 2026 06:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786688766; cv=none; b=bqhv/H6QncZ85KbiCRBUpoHrO7jMEEhuLV5fZM9jod/O6XZi5UcjjavXowybOIMLj4GgR6aQkFf9/pZCgRdivWOv9Q2n7TyvDw1bqxOycHYQzaq3N4vIo5tpCg9wIDHFhXgE4suEM7+9ino9/kHSar7XeNIC/7L0z8NbP1aDOxI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786688766; c=relaxed/simple; bh=tivZ5BYNFH4W6I41+vAAaK6MuTK6IPDTNH6UPZleqPQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hKWb7NK8WcYVkSsXOuP8SVmityR1dJkOIR567zGDWmpCx2+6LTMNpFqhmkANhi7qc8fK70sqGxEIqoiIlthDbhfD5LEO5QtaExaEmCuh+JOFRIPO0HxGXONma228de91ca/cW3yn1rMkqzrjcrOXuki5lz2u3F2J+0zVUWBH5L0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Qx2YJx7X; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Qx2YJx7X" Received: by smtp.kernel.org (Postfix) with ESMTPS id 15DD9C2BCC7; Fri, 14 Aug 2026 06:26:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786688766; bh=tivZ5BYNFH4W6I41+vAAaK6MuTK6IPDTNH6UPZleqPQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Qx2YJx7X0+aP/+wYdJ83bvBXdHWsofmEBlSPjKCLlt2t7y4wyWw4MTERtWjETEhW2 Khasy0c8i6x0xHaocaAuzJ2ZFUwK64yDnwe0NUyvSHTHeOKtHCVoYifD47rNL/Sir+ wAb4oaA4yiAi/PSBtTtGSqopsePQicO0ZQ1BaHQlSXo8FSJQaa8hWdvXxEmJQAEGCc FH0T+r9egdMR+uF3jGcCec8eHaup+h7cw2XL7oFdVm6dtpNIWBgljcdgqRWVkW86Fb DFCRh6NrEY2k4kW5tjtulMWwfpn97Mwb71xYLSG/XTmwT4AFsCvRGfvJyqsnsf3yT3 tGdulo3DP9nAA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E75DEC5CFC1; Fri, 14 Aug 2026 06:26:05 +0000 (UTC) From: Long Zhao via B4 Relay Date: Fri, 14 Aug 2026 14:25:41 +0800 Subject: [PATCH v4 1/4] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260814-cv75-v4-b-v4-1-ef2e83ec0eac@ambarella.com> References: <20260814-cv75-v4-b-v4-0-ef2e83ec0eac@ambarella.com> In-Reply-To: <20260814-cv75-v4-b-v4-0-ef2e83ec0eac@ambarella.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Long Zhao X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786688763; l=6392; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=nKtxPce2re61fXy+1qoLhWBCtRzuGBLrRckpr8oXxx4=; b=a7znp/pnlWhAgzN3TRpcMoERgnBeJ920ph/HZ3tle3KxQfiUaFKl2AmqV2MRDJtnfcFK+/YGm wp4iv38A6uABsR90+2KY7ZgmwIvmDZIXGRtupCgw+X3z5W3aa74riJC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 pin controller binding using generic function and groups properties for pinmux configuration. Signed-off-by: Long Zhao --- .../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 240 +++++++++++++++++++++ 1 file changed, 240 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml new file mode 100644 index 000000000000..9d65da32d3d2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 Pin Controller + +maintainers: + - Long Zhao + +description: + The Ambarella CV75 pin controller configures pin multiplexing, bias and + drive strength for the main GPIO banks. Pin groups and their mux settings + are defined by the pin controller driver and selected by function and group + names. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: ambarella,cv75-pinctrl + + reg: + maxItems: 1 + description: IOMUX registers + + ambarella,drive-strength-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: RCT syscon containing the drive-strength registers. + + ambarella,pull-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Secure scratchpad syscon containing the pull registers. + +patternProperties: + "^[a-z0-9-]+-pins$": + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - can0 + - can1 + - clk_au + - dmic0 + - enet0 + - hsync0 + - hsync1 + - i2c0 + - i2c1 + - i2c2 + - i2c3 + - i2cs + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm6 + - pwm7 + - pwm8 + - pwm9 + - pwm10 + - pwm11 + - sdmmc0 + - sdmmc1 + - snand + - spi0 + - spi1 + - spi2 + - spi3 + - spi_slave + - spinor + - uart0 + - uart1 + - uart2 + - uart3 + - uart4 + - vin_master_sync + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt + + groups: + $ref: /schemas/types.yaml#/definitions/string-array + items: + enum: + - can0 + - can1 + - clk_au + - dmic0 + - enet_2nd_ref_clk_a + - enet_2nd_ref_clk_b + - enet_ext_osc_clk + - enet0_ptp_pps_o + - hsync0 + - hsync1 + - i2c0_a + - i2c0_b + - i2c1_a + - i2c1_b + - i2c2 + - i2c3_a + - i2c3_b + - i2c3_c + - i2cs_a + - i2cs_b + - i2cs_c + - i2cs_d + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4_a + - pwm4_b + - pwm5_a + - pwm5_b + - pwm6_a + - pwm6_b + - pwm7_a + - pwm7_b + - pwm8_a + - pwm8_b + - pwm9_a + - pwm9_b + - pwm10_a + - pwm10_b + - pwm11_a + - pwm11_b + - rgmii0 + - rmii0 + - sdmmc0_1bit + - sdmmc0_4bit + - sdmmc0_cd + - sdmmc0_hs_sel + - sdmmc0_reset + - sdmmc0_wp + - sdmmc1_1bit + - sdmmc1_4bit + - sdmmc1_cd + - sdmmc1_hs_sel + - sdmmc1_reset + - sdmmc1_wp + - snand + - spi0 + - spi1 + - spi2 + - spi3_a + - spi3_b + - spi3_c + - spi_slave_a + - spi_slave_b + - spi_slave_c + - spi_slave_d + - spi_slave_e + - spinor + - uart0 + - uart1 + - uart1_flow + - uart2_a + - uart2_b + - uart2_c + - uart2_flow_a + - uart2_flow_b + - uart3_a + - uart3_b + - uart3_flow_a + - uart3_flow_b + - uart4_a + - uart4_b + - uart4_flow_a + - uart4_flow_b + - vin_master_sync_a + - vin_master_sync_b + - vin_master_sync_c + - vin_master_sync_d + - vin_master_sync_e + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt_a + - wdt_b + - wdt_c + - wdt_d + - wdt_e + - wdt_f + minItems: 1 + maxItems: 6 + uniqueItems: true + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + drive-strength: + enum: [3, 4, 5, 6, 7, 8, 9, 12] + + required: + - function + - groups + +required: + - compatible + - reg + - ambarella,drive-strength-syscon + - ambarella,pull-syscon + +unevaluatedProperties: false + +examples: + - | + pinctrl: pinctrl@e4010000 { + compatible = "ambarella,cv75-pinctrl"; + reg = <0xe4010000 0x1000>; + ambarella,drive-strength-syscon = <&rct>; + ambarella,pull-syscon = <&scratchpad>; + + uart0-pins { + function = "uart0"; + groups = "uart0"; + bias-disable; + drive-strength = <8>; + }; + }; -- 2.34.1