Re: [PATCH v3 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Device Tree node overrides by label are not sorted alphabetically in `ipq5210-rdp504.dts`.
--

--- Patch [11]: [PATCH v3 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node ---
commit 0ce1f4dcc02ba914d9905f5b322a335147cf2ae6
Author: Luo Jie <jie.luo@oss.qualcomm.com>

arm64: dts: qcom: ipq5210: Add CMN PLL device node

This commit adds the CMN PLL node for enabling output clocks to the
networking hardware blocks on IPQ5210 devices. The reference clock
is routed from XO to the CMN PLL through the WiFi block.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> index 941f866ecfe95..7410d092814e5 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts
> @@ -74,6 +74,21 @@ &uart1 {
>  	status = "okay";
>  };
>  
> +/*
> + * The bootstrap pins for the board select the XO clock frequency that
> + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
> + * enables the right dividers, to ensure the reference clock output
> + * from WiFi to the CMN PLL is 48 MHZ.
> + */
> +&ref_48mhz_clk {

[Severity: Low]
This isn't a bug, but should the device tree node overrides be sorted
alphabetically by label?

It looks like &ref_48mhz_clk is placed after &uart1. Placing it earlier
in the file would maintain the standard alphabetical ordering expected in
Qualcomm device tree files.

> +	clock-div = <1>;
> +	clock-mult = <1>;
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com?part=11