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([2a0a:ef40:f1b:d401:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49996106c6esm100527875e9.5.2026.08.16.12.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Aug 2026 12:42:10 -0700 (PDT) From: Dawid Olesinski To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Diederik de Haas , Eric Biggers , Sebastian Reichel , Philipp Zabel , Conor Dooley , Corentin Labbe , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH v3 4/4] arm64: dts: rockchip: Add crypto node to rk3588-base Date: Sun, 16 Aug 2026 20:39:47 +0100 Message-ID: <20260816194112.552100-5-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260816194112.552100-1-dawidro@gmail.com> References: <20260708175837.1718437-1-dawidro@gmail.com> <20260816194112.552100-1-dawidro@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the device tree node for the V2 cryptographic hardware accelerator on RK3588. On RK3588 the crypto IP sits inside the secure domain controlled by SECURECRU, a register bank that is exclusively accessible to the TrustZone firmware (TF-A). Linux must therefore obtain its clocks and reset line through the ARM SCMI interface provided by the firmware rather than mapping the CRU registers directly. Attempting direct MMIO access to SECURECRU from the non-secure world triggers an asynchronous bus fault. The interrupt uses the four-cell GICv3 format as required by the RK3588 GIC node definition (the fourth cell is the CPU affinity/partition specifier; 0 means no affinity constraint). The node is disabled by default; board files that wish to use hardware crypto offload must enable it. Co-developed-by: Corentin Labbe Signed-off-by: Corentin Labbe Signed-off-by: Dawid Olesinski Tested-by: Diederik de Haas # Quartz64-B, NanoPi R5S, NanoPC-T6 LTS --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 4fb8888c281c..980c345a5de0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2249,6 +2249,17 @@ sdhci: mmc@fe2e0000 { status = "disabled"; }; + crypto: crypto@fe370000 { + compatible = "rockchip,rk3588-crypto", "rockchip,rk3568-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, + <&scmi_clk SCMI_HCLK_SECURE_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&scmi_reset SCMI_SRST_CRYPTO_CORE>; + reset-names = "core"; + }; + rng@fe378000 { compatible = "rockchip,rk3588-rng"; reg = <0x0 0xfe378000 0x0 0x200>; -- 2.47.3