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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000026CA.mail.protection.outlook.com (10.167.244.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.339.3 via Frontend Transport; Mon, 17 Aug 2026 02:39:44 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 16 Aug 2026 21:39:43 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Sun, 16 Aug 2026 21:39:42 -0500 Received: from xhdlc250058.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.45 via Frontend Transport; Sun, 16 Aug 2026 21:39:39 -0500 From: Sai Krishna Musham To: , , , , , , , CC: , , , , , , , Subject: [PATCH v5 1/2] dt-bindings: PCI: amd-mdb: Add CPM6 support Date: Mon, 17 Aug 2026 08:09:31 +0530 Message-ID: <20260817023932.1743100-2-sai.krishna.musham@amd.com> X-Mailer: git-send-email 2.44.4 In-Reply-To: <20260817023932.1743100-1-sai.krishna.musham@amd.com> References: <20260817023932.1743100-1-sai.krishna.musham@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026CA:EE_|CYYPR12MB8923:EE_ X-MS-Office365-Filtering-Correlation-Id: f8989ad8-ac8a-4c91-0c6f-08defc08cc40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|7416014|376014|36860700016|22082099003|18002099003|56012099006|3023799007|13003099007|6133799003|11063799006|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gglUGg1lXUQ4R42DWEe8snYcyp+Md7C9VzZCoqlemdbyPem8+4M+yS4dT/M1321poYkGIK1HWrPEMxVw0QRN54YMqJgOaZmcwqjTXBXJLsKTc3uNOipByAoc1+OXl+ETzhT3oKabaTi03tuek3QSaVT+eHDRZL8kRSfR+asHglzfwQMS+ARMA3H9v6sP6XMZLqamK+nLl5AaWVabZxfe96fgIBkNUyzijEYC75FJvI+fSOhFP3zTC4bofZ5DzsqhGDfZFGshq8fYB22m0gqpCiRdWPC2J4kgJbQYqhVdM7Xbhzxk/gQieafa92rdVRNMZwYmMdsBSN3elQFHXBeEPACJlgOc/UuGS3Y+IK4JRReYpzIi6gayMvLbSJNQ8bVNN8eOQ+WECiS/DdGqKdbhvATkVMd//TkGpRkymcTP52qWAWSvEbe148EPACchmDDM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2026 02:39:44.9130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8989ad8-ac8a-4c91-0c6f-08defc08cc40 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026CA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8923 The AMD CPM6 PCIe controller is based on the Synopsys DesignWare PCIe IP and integrates two PCIe host controller instances. Add the "amd,versal2-cpm6-host" and "amd,versal2-cpm6-host1" compatible strings to describe the HOST0 and HOST1 controller instances. Add "intr" to the vendor-specific reg-names in snps,dw-pcie.yaml for the per-controller interrupt register region used by CPM6. Update amd,versal2-mdb-host.yaml with separate register definitions: - MDB5: 4 regions (slcr, config, dbi, atu) - CPM6: 5 regions (slcr, config, dbi, atu, intr) Signed-off-by: Sai Krishna Musham --- Changes in v5: - Explain host vs host1 in the commit message. - Drop redundant minItems for MDB5 (4 is already min). - Drop redundant maxItems for CPM6 (5 is already max). Changes in v4: - None Changes in v3: - Update subject to match history. - Move allOf to the end, after required block. - Drop the CPM6 example. Changes in v2: - Update the CPM6 device tree binding and example. v1 https://lore.kernel.org/all/20260402180006.486229-2-sai.krishna.musham@amd.com/ v2 https://lore.kernel.org/all/20260728202044.1785986-2-sai.krishna.musham@amd.com/ v3 https://lore.kernel.org/all/20260803144412.713639-2-sai.krishna.musham@amd.com/ v4 https://lore.kernel.org/all/20260808105256.3705889-2-sai.krishna.musham@amd.com/ --- .../bindings/pci/amd,versal2-mdb-host.yaml | 41 ++++++++++++++++--- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 + 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 406c15e1dee1..cd207b346313 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -9,27 +9,30 @@ title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller maintainers: - Thippeswamy Havalige -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - - $ref: /schemas/pci/snps,dw-pcie.yaml# - properties: compatible: - const: amd,versal2-mdb-host + enum: + - amd,versal2-mdb-host + - amd,versal2-cpm6-host + - amd,versal2-cpm6-host1 reg: + minItems: 4 items: - description: MDB System Level Control and Status Register (SLCR) Base - description: configuration region - description: data bus interface - description: address translation unit register + - description: CPM6 PCIe error and event interrupt registers reg-names: + minItems: 4 items: - const: slcr - const: config - const: dbi - const: atu + - const: intr ranges: maxItems: 2 @@ -92,6 +95,34 @@ required: - "#interrupt-cells" - interrupt-controller +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: amd,versal2-mdb-host + then: + properties: + reg: + maxItems: 4 + reg-names: + maxItems: 4 + - if: + properties: + compatible: + contains: + enum: + - amd,versal2-cpm6-host + - amd,versal2-cpm6-host1 + then: + properties: + reg: + minItems: 5 + reg-names: + minItems: 5 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index b3216141881c..21f86609ddb6 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -117,6 +117,8 @@ properties: enum: [ ecam ] - description: AMD MDB PCIe SLCR region const: slcr + - description: AMD CPM6 PCIe error and event interrupt registers + const: intr allOf: - contains: enum: [ dbi, ctrl ] -- 2.44.4