From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E25064519AD; Tue, 18 Aug 2026 10:32:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787049134; cv=none; b=WAMK4lkMp3Is8CBkibWI5wjRYGf4bsY1Je4tSqZtXV6WPioL3N5AB5QSFEVyNeBcHYAuPpri/objUxINxEim1JuwhpUX0o/DSPdIEs43X9XECN6XWSfyB92B51kKX7prggZXPyvMrhBfka0c7DIzr1kwZqG0wX5XQwFpJuff4qs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787049134; c=relaxed/simple; bh=8kmXgMn7RPN9j9Jy9UOQa6siDtddsJcy9fJ+5E1nz2k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FDjPTkYJc7uFsmRe2YJM2+FQF5R/K2/xZHURU0R2aBioL5gv6s39fxXxC7ajTJcCtapj2v+o4ADHe51b5M01UZl41iaFH56QgF5ovnQtJ6aLjqSFjo2KRwUImEVnndOWGUfJjEbDV1ptgvL7UsNFFbJuh4XfamOSs4hhxjCe1dY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d7hlcV7q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d7hlcV7q" Received: by smtp.kernel.org (Postfix) with ESMTPS id A314BC2BCFB; Tue, 18 Aug 2026 10:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1787049133; bh=8kmXgMn7RPN9j9Jy9UOQa6siDtddsJcy9fJ+5E1nz2k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=d7hlcV7qh1C9Zlu6p9j2r0LEu4/yFtH5BfZx8xE5ZzFWJ0mm8N1efoD151U5T/Lq6 GT0Q7Q2yS60HFyOYAjgfbmtAPJjQp6Gvbv73Mk7F8FgnvIdMzv0LBgOHwGXYszZWMk Y++nOMT37eS8o8WoJPoD5iudbpS/D51h+ZD8d1X/SCX3NrmXoSXslUF5rVMZZb9PbE IrVrryimvRO29HhA75yBQ60SS0n+H/bHauxNgboORIQMrPXmr+aA0vCu6dL1Zl3TD/ Z/yh06+hRuQxuGWRrL/ZOXSTiU9FBREauzG8qLV34o725gC1Ih9S2L2tO7wLVKX40R B+N9OswQ/AXPg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87A2AC5DF83; Tue, 18 Aug 2026 10:32:13 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 18 Aug 2026 18:31:17 +0800 Subject: [PATCH v5 03/12] dt-bindings: clock: add Ambarella CV75 RCT Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260818-cv75-v5-v5-3-7bbb12f0360f@ambarella.com> References: <20260818-cv75-v5-v5-0-7bbb12f0360f@ambarella.com> In-Reply-To: <20260818-cv75-v5-v5-0-7bbb12f0360f@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney , Lee Jones , mfd@lists.linux.dev, Long Zhao , Long Zhao X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787049131; l=2831; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=V/+hOnSzFSfW8h7vb5mU8wEcrovus3c1ZYvtQiEoZ8M=; b=1L9RzEZpAKZpbuE1EZVlaJ604mA6VtWntg5JCP8Rhm6MWZdE0JW3z43uEuTH1cwtS0XxbPUvA aWZqdUcvDKWCa58iV/FqZnZQ0lyieXXzk8z42eNT25wWrFJaiCnnOgI X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 RCT clock controller and the clock ID header used by DT consumers. This initial binding describes only the clock-provider functionality. Reset-controller support is outside scope of this series, so #reset-cells property is intentionally omitted. Signed-off-by: Long Zhao --- .../bindings/clock/ambarella,cv75-rct.yaml | 58 ++++++++++++++++++++++ include/dt-bindings/clock/ambarella,cv75-rct.h | 15 ++++++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml new file mode 100644 index 000000000000..eb5956fc32bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 RCT Clock Controller + +maintainers: + - Long Zhao + +description: | + The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides + PLLs, clock muxes and dividers for on-chip peripherals. + + The same register region is also exposed as a syscon for other SoC + blocks (e.g. pin drive-strength), hence the "syscon" compatible. + + Clock indices are defined in include/dt-bindings/clock/ambarella,cv75-rct.h. + +properties: + + compatible: + items: + - const: ambarella,cv75-rct + - const: syscon + + reg: + maxItems: 1 + + clocks: + description: Reference crystal oscillator (typically 24 MHz) + maxItems: 1 + + clock-names: + const: osc + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ed080000 { + compatible = "ambarella,cv75-rct", "syscon"; + reg = <0xed080000 0x1000>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/ambarella,cv75-rct.h b/include/dt-bindings/clock/ambarella,cv75-rct.h new file mode 100644 index 000000000000..0a6e946c9108 --- /dev/null +++ b/include/dt-bindings/clock/ambarella,cv75-rct.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H +#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H + +/* Boot / bus clocks */ +#define CV75_GCLK_UART0 0 +#define CV75_GCLK_CORE 1 +#define CV75_GCLK_AHB 2 +#define CV75_GCLK_APB 3 + +#endif -- 2.34.1