From: sashiko-bot@kernel.org
To: "Vishnu Reddy" <busanna.reddy@oss.qualcomm.com>
Cc: robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org,
media-ci@linuxtv.org
Subject: Re: [PATCH v2 4/5] media: iris: Fix power-off ordering to disable power domain after clocks
Date: Tue, 18 Aug 2026 16:05:12 +0000 [thread overview]
Message-ID: <20260818160512.BC1F11F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260818-iris-fixes-dma-pseq-fint-v2-4-8dc8c4b3880e@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The patch fixes the clock/power domain disable sequence in `iris_vpu_power_off_hw()` but misses identical sequence bugs in `iris_vpu35_power_off_hw()` and `iris_vpu33_power_off_controller()`, leaving them to operate on unpowered clock controllers.
--
--- Patch [4]: [PATCH v2 4/5] media: iris: Fix power-off ordering to disable power domain after clocks ---
commit f43aeec1ae78e41029af71f7d7db01a62fedc472
Author: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
media: iris: Fix power-off ordering to disable power domain after clocks
This commit fixes the power-off ordering in iris_vpu_power_off_hw() to
ensure clocks are disabled before the associated power domain is removed,
preventing unpredictable behavior or hardware hangs.
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index e4847c1077097..3cd493b06d84c 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -223,10 +223,10 @@ int iris_vpu_power_off_controller(struct iris_core *core)
> void iris_vpu_power_off_hw(struct iris_core *core)
> {
> dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
> - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
> iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> }
[Severity: High]
This is a pre-existing issue and was not introduced by this patch, but does
this same ordering problem exist in
drivers/media/platform/qcom/iris/iris_vpu3x.c?
Looking at iris_vpu33_power_off_controller(), IRIS_CTRL_POWER_DOMAIN is
removed before disabling IRIS_AXI_CLK:
disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
Similarly, in iris_vpu35_power_off_hw(), iris_vpu33_power_off_hardware()
removes the domain before IRIS_HW_FREERUN_CLK and IRIS_AXI_CLK are disabled:
iris_vpu33_power_off_hardware(core);
iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
Should these paths also be updated to prevent operating on unpowered clock
controllers and causing system hangs on device teardown?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260818-iris-fixes-dma-pseq-fint-v2-0-8dc8c4b3880e@oss.qualcomm.com?part=4
next prev parent reply other threads:[~2026-08-18 16:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-18 15:54 [PATCH v2 0/5] media: iris: Fix DMA coherency, power-off ordering, and frame interval issues Vishnu Reddy
2026-08-18 15:54 ` [PATCH v2 1/5] media: iris: Add dma sync calls for input and output buffers Vishnu Reddy
2026-08-18 16:03 ` sashiko-bot
2026-08-18 15:54 ` [PATCH v2 2/5] dt-bindings: media: qcom,sc7280-venus: Add dma-coherent property Vishnu Reddy
2026-08-18 15:54 ` [PATCH v2 3/5] arm64: dts: qcom: sc7280: Add dma-coherent property into venus node Vishnu Reddy
2026-08-18 15:54 ` [PATCH v2 4/5] media: iris: Fix power-off ordering to disable power domain after clocks Vishnu Reddy
2026-08-18 16:05 ` sashiko-bot [this message]
2026-08-18 15:54 ` [PATCH v2 5/5] media: iris: Fix frame interval enumeration for non-divisor framerates Vishnu Reddy
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