Re: [PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message inaccurately claims to modify the 'CPU address', but the code actually modifies the PCIe bus address.
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--- Patch [2]: [PATCH v1 2/3] arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap ---
commit e35c73490a85a542f882f45cf6fb1b821101d403
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx94: Avoid 32-bit pcie window system ram overlap

This commit addresses a memory overlap issue between the PCIe non-prefetchable
memory and system RAM. It adjusts the address space configuration in the imx94
device tree to use a reserved, safe range.

> diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx94.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
> @@ -1379,7 +1379,7 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> -				 <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>,
> +				 <0x82000000 0x0 0x10000000 0x9 0xe0000000 0x0 0x10000000>,

[Severity: Medium]
The commit message states "Move the PCIe non-prefetchable memory CPU address
from 0xe0000000 to 0x10000000". Is this description accurate?

Looking at the Device Tree ranges property format:
<child-bus-address> <parent-bus-address> <length>

The 4th and 5th cells representing the parent (CPU) address (0x9 0xe0000000)
remain unchanged here. The third cell (the low 32 bits of the PCIe bus
address) is being modified from 0xe0000000 to 0x10000000.

Could the commit message be updated to correctly reflect that the PCIe bus
address is being changed rather than the CPU address?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260820083620.877251-1-hongxing.zhu@oss.nxp.com?part=2