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b=PniMze+hrYQ9u0aKFFo/rW7MheGFY/zwzh1EtP7m/zKDQ3EVR/tnvhx+jyXxmDt5m2z9HLl8fDY3XlUWdI7DyS+eRAz4kCkvwZz46bXF9+9TEbK5VWJIpMqppYw/ZNYc3fmEXPkRVsJE3ymjCfRjalM1uk0zbekYkBsePD7BUqUtW80P9wdb2OesqpoE73BCGF1k2LsL/sJWXIOCp6nbyScSePM+XG4Qyu9k4hg+vXcfITJeOQqTThzuZNPuF6jW7iAveBrRpZ86UOI0Qcr0SRQX+RYLo2lbg6B1AGFZQpCh8UQFPFp2zfJNsczgLZNsgalB79Tgw5yzA2zR5cKAAQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=altera.com; Received: from DM4PR03MB6208.namprd03.prod.outlook.com (2603:10b6:5:39c::19) by BLAPR03MB5636.namprd03.prod.outlook.com (2603:10b6:208:297::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.339.10; Thu, 20 Aug 2026 18:57:47 +0000 Received: from DM4PR03MB6208.namprd03.prod.outlook.com ([fe80::2216:93ef:67b:9e04]) by DM4PR03MB6208.namprd03.prod.outlook.com ([fe80::2216:93ef:67b:9e04%3]) with mapi id 15.21.0339.008; Thu, 20 Aug 2026 18:57:47 +0000 From: Tanmay Kathpalia To: linux-mmc@vger.kernel.org Cc: ulfh@kernel.org, adrian.hunter@intel.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org, p.zabel@pengutronix.de, devicetree@vger.kernel.org, Tanmay Kathpalia , linux-kernel@vger.kernel.org Subject: [PATCH v5 8/8] mmc: sdhci-cadence: add Altera Agilex5 SD6HC support Date: Thu, 20 Aug 2026 11:57:14 -0700 Message-Id: <20260820185721.22823-9-tanmay.kathpalia@altera.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20260820185721.22823-1-tanmay.kathpalia@altera.com> References: <20260820185721.22823-1-tanmay.kathpalia@altera.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SJ0PR03CA0385.namprd03.prod.outlook.com (2603:10b6:a03:3a1::30) To DM4PR03MB6208.namprd03.prod.outlook.com (2603:10b6:5:39c::19) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR03MB6208:EE_|BLAPR03MB5636:EE_ X-MS-Office365-Filtering-Correlation-Id: bc0cfd41-5f61-4022-7696-08defeecec8d X-MS-Exchange-AtpMessageProperties: SA X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|23010399003|10067099003|11063799006|56012099006|6133799003|18002099003|22082099003|55112099003; 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The SoC requires three named resets: "sdhc-reset", "combophy", and "sdmmc-ocp". All three are exclusive and must be asserted together before being released, so the SDHCI, SoftPHY, and OCP/AXI clock domains cross the reset boundary simultaneously. SoftPHY is shared with NAND at the SoC level, but only one of SDMMC or NAND is enabled on a given board. The IOMMU maps DMA addresses within a 40-bit physical address space, so the DMA mask is capped at 40 bits to prevent allocation beyond the controller's reach. The silicon requires the MULTIBLOCK_READ_ACMD12, CAP_CLOCK_BASE_BROKEN, PRESET_VALUE_BROKEN, and ACMD23_BROKEN quirks. Since CAP_CLOCK_BASE_BROKEN prevents reading the base clock from the capabilities register, the maximum clock is supplied from the platform clock instead. Signed-off-by: Tanmay Kathpalia Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-cadence-core.c | 85 +++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence-core.c b/drivers/mmc/host/sdhci-cadence-core.c index 18a5329f27db..e215f6a4c344 100644 --- a/drivers/mmc/host/sdhci-cadence-core.c +++ b/drivers/mmc/host/sdhci-cadence-core.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -90,6 +91,7 @@ struct sdhci_cdns4_phy_cfg { struct sdhci_cdns_drv_data { int (*init)(struct platform_device *pdev); const struct sdhci_pltfm_data pltfm_data; + u64 dma_mask; }; static const struct sdhci_cdns4_phy_cfg sdhci_cdns4_phy_cfgs[] = { @@ -196,6 +198,23 @@ static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host) return host->max_clk; } +static int sdhci_cdns_set_dma_mask(struct sdhci_host *host) +{ + const struct sdhci_cdns_drv_data *data; + struct device *dev = mmc_dev(host->mmc); + int ret; + + data = of_device_get_match_data(dev); + if (!data || !data->dma_mask) + return 0; + + ret = dma_set_mask_and_coherent(dev, data->dma_mask); + if (ret) + return dev_err_probe(dev, ret, "failed to set DMA mask\n"); + + return 0; +} + static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) { u32 tmp; @@ -462,6 +481,44 @@ static int elba_drv_init(struct platform_device *pdev) return 0; } +static int sdhci_cdns6_agilex5_init(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct reset_control_bulk_data resets[] = { + { .id = "sdhc-reset" }, + { .id = "combophy" }, + { .id = "sdmmc-ocp" }, + }; + int ret; + + /* + * Assert SDHCI, SoftPHY (combophy), and SDMMC OCP/AXI resets together + * so their active periods overlap before all domains are released. + * SoftPHY is shared with NAND, but only one of SDMMC + * or NAND is enabled on a given board. + */ + ret = reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(resets), resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); + + ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets); + if (ret) { + dev_err_probe(dev, ret, "failed to assert resets\n"); + goto out_put; + } + + /* Hold resets asserted long enough for all clock domains to capture. */ + usleep_range(10, 20); + + ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); + if (ret) + dev_err_probe(dev, ret, "failed to deassert resets\n"); + +out_put: + reset_control_bulk_put(ARRAY_SIZE(resets), resets); + return ret; +} + static const struct sdhci_ops sdhci_cdns4_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -481,6 +538,18 @@ static const struct sdhci_ops sdhci_cdns6_ops = { .hw_reset = sdhci_cdns6_hw_reset, }; +static const struct sdhci_ops sdhci_cdns6_agilex5_ops = { + .set_clock = sdhci_cdns6_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .platform_execute_tuning = sdhci_cdns_execute_tuning, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, + .hw_reset = sdhci_cdns6_hw_reset, + .set_dma_mask = sdhci_cdns_set_dma_mask, +}; + static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { .pltfm_data = { .ops = &sdhci_cdns4_ops, @@ -508,6 +577,18 @@ static const struct sdhci_cdns_drv_data sdhci_cdns4_drv_data = { }, }; +static const struct sdhci_cdns_drv_data sdhci_cdns6_agilex5_drv_data = { + .init = sdhci_cdns6_agilex5_init, + .pltfm_data = { + .ops = &sdhci_cdns6_agilex5_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ACMD23_BROKEN, + }, + .dma_mask = DMA_BIT_MASK(40), +}; + static const struct sdhci_cdns_drv_data sdhci_cdns6_drv_data = { .pltfm_data = { .ops = &sdhci_cdns6_ops, @@ -713,6 +794,10 @@ static const struct of_device_id sdhci_cdns_match[] = { .compatible = "cdns,sd4hc", .data = &sdhci_cdns4_drv_data, }, + { + .compatible = "altr,agilex5-sd6hc", + .data = &sdhci_cdns6_agilex5_drv_data, + }, { .compatible = "cdns,sd6hc", .data = &sdhci_cdns6_drv_data, -- 2.43.7