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charset="UTF-8" Content-Transfer-Encoding: 8bit X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: G7DrPL2g_jS71LPHl0pTIHkUTbfIdUW_ X-Proofpoint-GUID: G7DrPL2g_jS71LPHl0pTIHkUTbfIdUW_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODIxMDE0MyBTYWx0ZWRfX+SGOslq2FMrF 4kYNRDJKKlK11G8p+Flrh3DODYSGVWw/31+EkoPPyOQq9i/m484kWcdd78tWu72Z7sFra8TNzly P3mnquozqjlAfchx7qQj+QS+Y+fAzaqciJvg+TLeqoZPGr6YyAXI X-Authority-Analysis: v=2.4 cv=fcCdDUQF c=1 sm=1 tr=0 ts=6a88940c cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=bGhLtI4Elc35aERHuvsA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODIxMDE0MyBTYWx0ZWRfX1aQmuyS5AHtJ yzVm7iAl9e0iny0j+nhWJrlFvaLd9tbVxA1bBJvAL/ESLmv1IJEScc+LK8y/Ea2kviKJYFn+awj 63AeAgRPo45Ts6AhUqIuSrqZH1t5nuA4pU+R2ODO0KFq7o+UqXAT8lhx2k2gdZOPXqPsGPCGY0I zHkgUYUguPFNTji6oMVKzKbmqGYLY9HsMb9haut4uCgrIADxvtQ8gbAA3xqxuVeUyaXWe6nXwQW +2BR9EYHUQd0lMz5ekV7xI5zblgNBw56hqiQ2dBL1uvV90U+GsqbTSF1gjjGE6sX8Zfuld6qlUM x8kaZwrPgx4zqhPvwcsSgij519mLCzTAVJvPmqyZFaPCKp1EFwxGRHpO25U6RfsMK+legS/0OtH rtr/sp1+uzVYLyAYtS28ellPXVdW9etzVZ94e3HApDiEwUnEwQMyuzZUKl0L2qWlBZ8UwIJCZpL CeKsJT0GcMWQQ+JhyaQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-21_06,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608210143 The ADXL367 exposes two independent interrupt output pins, INT1 and INT2, each with its own event mapping register. The driver has always hardcoded INT1, so a board that routes only INT2 to the host never receives interrupts. This series lets the driver pick the interrupt map register based on the interrupt-names device tree property. v3 addresses review feedback on the driver patch: the interrupt number returned by fwnode_irq_get_byname() is now used for the request, so the requested line always matches the routed INTMAP register even if the interrupts are listed in an unexpected order. A precursor patch converts the existing regmap_update_bits(..., en ? mask : 0) helpers to regmap_assign_bits() as suggested during review. Changes in v3: - New precursor patch converting the boolean regmap_update_bits() helpers to regmap_assign_bits(). - Use the fwnode_irq_get_byname() interrupt number for devm_request_threaded_irq() in the INT2 patch. - Rebased on the latest togreg/testing. Antoniu Miclaus (4): dt-bindings: iio: update unreachable maintainer entries dt-bindings: iio: accel: adi,adxl367: add interrupt-names iio: accel: adxl367: use regmap_assign_bits() iio: accel: adxl367: add support for INT2 interrupt pin .../bindings/iio/accel/adi,adxl367.yaml | 13 ++++- .../bindings/iio/adc/adi,ad4130.yaml | 3 +- .../bindings/iio/addac/adi,ad74115.yaml | 3 +- .../bindings/iio/addac/adi,ad74413r.yaml | 3 +- MAINTAINERS | 4 ++ drivers/iio/accel/adxl367.c | 47 +++++++++++++++---- 6 files changed, 60 insertions(+), 13 deletions(-) base-commit: 350d1fb9204b13c5f95e511e98b8bcb47574d425 -- 2.43.0