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([2406:b400:53:4f23:d4ee:2200:a28b:c285]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-395e49d8d26sm2171183a91.10.2026.08.22.02.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Aug 2026 02:39:17 -0700 (PDT) From: Udaya Kiran Challa To: angelogioacchino.delregno@collabora.com, matthias.bgg@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, me@brighamcampbell.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Udaya Kiran Challa , Krzysztof Kozlowski Subject: [PATCH v5] dt-bindings: arm: mediatek: mediatek,g3dsys: Convert to DT schema Date: Sat, 22 Aug 2026 15:08:29 +0530 Message-Id: <20260822093829.46295-1-challauday369@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the MediaTek G3D system controller devicetree binding from the legacy text format to DT schema. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Udaya Kiran Challa --- Changelog: Changes since v4: - Add Mediatek Soc maintainers in the send list Link to v4:https://lore.kernel.org/all/20260326181726.64957-1-challauday369@gmail.com/ Changes since v3: - Fix $id path to match new location Link to v3:https://lore.kernel.org/all/20260325181509.3430-1-challauday369@gmail.com/ Changes since v2: - Move binding to soc/mediatek directory - Rename file to mediatek,mt2701-g3dsys.yaml based on fallback compatible Link to v2:https://lore.kernel.org/all/20260323180616.23333-1-challauday369@gmail.com/ Changes since v1: - Drop redundant description for reg - Drop redundant description for provider properties Link to v1:https://lore.kernel.org/all/20260315080302.454233-1-challauday369@gmail.com/ --- .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ---------- .../soc/mediatek/mediatek,mt2701-g3dsys.yaml | 58 +++++++++++++++++++ 2 files changed, 58 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt deleted file mode 100644 index 7de43bf41fdc..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt +++ /dev/null @@ -1,30 +0,0 @@ -MediaTek g3dsys controller -============================ - -The MediaTek g3dsys controller provides various clocks and reset controller to -the GPU. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-g3dsys", "syscon": - for MT2701 SoC - - "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon": - for MT7623 SoC -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The g3dsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -g3dsys: clock-controller@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml new file mode 100644 index 000000000000..ad3df062d5db --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mt2701-g3dsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek G3D System Controller + +maintainers: + - Sean Wang + - Ryder Lee + +description: | + The MediaTek G3D system controller provides clocks and reset control + for the GPU subsystem on MediaTek SoCs. + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt2701-g3dsys + - const: syscon + - items: + - const: mediatek,mt7623-g3dsys + - const: mediatek,mt2701-g3dsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + g3dsys: syscon@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; -- 2.34.1