Re: [PATCH] arm64: dts: lx2160a: fix incorrect pinmux

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] The pinctrl offset for `dspi2_miso_mosi_pins` is set to `0x3`, which is unaligned for a 32-bit register width, triggering a synchronous alignment fault on ARM64.
- [High] Pinmux nodes `i2c0_pins` and `gpio0_3_2_pins` specify an incomplete 1-bit mask (`0x1 << 10`), causing the `pinctrl-single` driver to silently reject them.
--

--- Patch [1]: [PATCH] arm64: dts: lx2160a: fix incorrect pinmux ---
commit 361d41dcf4495f73be88ba1bf5234be91b377473
Author: Vincent Jardin <vjardin@free.fr>

arm64: dts: lx2160a: fix incorrect pinmux
    
For gpio1 value set for pinctrl is outside the mask and so will do
nothing. Add the missing offset for value field to be the same as the
mask as expected.

Fixes: 284ad7064aaa ("arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word")
Signed-off-by: Vincent Jardin <vjardin@free.fr>

> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 1d73abffa6b72..b9f079c49e193 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

[ ... ]

[Severity: High]
This isn't a bug introduced by this patch, but is the pinctrl offset unaligned
for dspi2_miso_mosi_pins?

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi:dspi2_miso_mosi_pins {
    ...
    pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
    ...
}

The pinctrl-single driver uses 32-bit accessors when the register width is 32.
Since the base offset is 0x3, this results in an unaligned I/O access on
arm64, which triggers a synchronous alignment fault.

Could this have been a typo for <0x0 (0x3 << 9) (0x7 << 9)>?

[Severity: High]
This is a pre-existing issue, but does this incomplete mask cause the pin
configuration to be skipped entirely?

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi:i2c0_pins {
    ...
    pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
    ...
}

This also appears in gpio0_3_2_pins:

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi:gpio0_3_2_pins {
    ...
    pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
    ...
}

Looking at the pinctrl-single driver, it strictly validates that the supplied
mask matches the hardware function mask shifted to the pin's bit position:

drivers/pinctrl/pinctrl-single.c:pcs_parse_bits_in_pinctrl_entry() {
    ...
    if (submask != mask_pos) {
        dev_warn(pcs->dev,
                "Invalid submask 0x%x for %pOFn at 0x%x\n",
                submask, np, offset);
        continue;
    }
    ...
}

Since the function mask is 0x7, mask_pos would be 0x1c00 (0x7 << 10), but the
supplied mask is 0x400 (0x1 << 10).

Because these do not match, does the driver log an invalid submask warning and
skip configuring the pin?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260824-for-upstream-lx2160a-pinmux-fix-v1-1-33a3c8d5ea8a@free.fr?part=1