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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-141861732f8sm21667830c88.10.2026.08.23.23.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Aug 2026 23:38:11 -0700 (PDT) From: Varadarajan Narayanan Date: Mon, 24 Aug 2026 12:07:44 +0530 Subject: [PATCH 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260824-phy-v1-4-257d68a3210b@oss.qualcomm.com> References: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> In-Reply-To: <20260824-phy-v1-0-257d68a3210b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: sIzEPm1wedO7xYLuN3JHj3SAVIpjz_0j X-Authority-Analysis: v=2.4 cv=U7iiy+ru c=1 sm=1 tr=0 ts=6a8be6d4 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=zXcBnA3yxj2v5e4wiOoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: sIzEPm1wedO7xYLuN3JHj3SAVIpjz_0j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfXwCpGQFtdiX17 gcY1wOGMf7WwxKWZ74IrUW86UsiJEskXE7Vw5PXt0I4zYFYJttks9M2vDRQptgnTQUQ0302N+RC K0/umq8gYFqXZ5ympCfk/3kMyVI3JTO/zijWvZ9RIPmrzrm8yMRfMtixgUdysPFziTwjudxjjgE AI8u/Ew9yE4QBxiqpbzi9u+TWRWLJoHxgdSnr4pFLwUYAbWQWUFsVfRr5jn8NWKI/Sh0g1DoTeW RkdG5+XTnCQyzysdV1+hvJ3s8Chgb5QL1neNgCCE9tlvjFU/m0OuUTjz5Eq018j9fXvp4I0E8L1 FLERUbmXcXVUk1AYgCcjZ65IcSa4s0Y4Vi8zZXq+YSusz1LHePQlee0er2dPgW/8GmUx7ysV/Gc TKVjXq9vICviKYZzDHKeDr+2JTijb9EqEGm/JTFf2ngvPWtavegUhQFboZyCfnQCgSyaTkFON9n iYRuPPML1dAIowJk8rQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA1NyBTYWx0ZWRfX9QMI5m/+jBMJ Gtasd1haff//NEDy8qsF2H9EzPa52RPOuR7AuDZAjFwccY1br0NMachthWx74VOSsDQaaTbVyUC Wh1bhTsYuvdLWMqv6RYj19zJM4QilQY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_02,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240057 The driver currently programs the common PHY register sequence directly in qcom_snps_hsphy_init(), with the fixed register writes split around the override parameter handling. This makes it hard to support SoCs that need a different sequence or different values. Move the fixed pre- and post-override register programming into per- compatible configuration tables, and keep the 7 nm override parameters in the same match-data structure. This allows the driver to share the common sequence while adding SoC-specific sequences for future platforms such as IPQ9650. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 120 ++++++++++++++++---------- 1 file changed, 74 insertions(+), 46 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 980ad1fb1e2e..5ffbe1a77dd4 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -104,6 +104,18 @@ struct phy_override_seq { u8 mask; }; +struct phy_reg_config { + u32 offset; + u32 mask; + u32 val; +}; + +struct phy_config_data { + const struct phy_reg_config *pre; + const struct override_param_map *override; + const struct phy_reg_config *post; +}; + #define NUM_HSPHY_TUNING_PARAMS (9) /** @@ -383,13 +395,42 @@ static const struct override_param_map sc7280_snps_7nm_phy[] = { {}, }; +static const struct phy_reg_config hs_5nm_phy_pre[] = { + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, POR }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, PLLBTUNE, PLLBTUNE }, + { USB2_PHY_USB_PHY_REFCLK_CTRL, REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, VBUSVLDEXTSEL0, VBUSVLDEXTSEL0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0 }, + { UINT_MAX, 0, 0 }, +}; + +static const struct phy_reg_config hs_5nm_phy_post[] = { + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N }, + { USB2_PHY_USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0 }, + { USB2_PHY_USB_PHY_UTMI_CTRL5, POR, 0 }, + { USB2_PHY_USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0 }, + { USB2_PHY_USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0 }, + { UINT_MAX, 0, 0 }, +}; + static int qcom_snps_hsphy_init(struct phy *phy) { struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); + const struct phy_config_data *data; + const struct phy_reg_config *tmp; int ret, i; dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); + data = of_device_get_match_data(hsphy->dev); + if (!data) + return -ENODEV; + ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); if (ret) return ret; @@ -414,24 +455,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) goto disable_clks; } - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, POR); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - FSEL_MASK, 0); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - PLLBTUNE, PLLBTUNE); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, - REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, - VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, - VBUSVLDEXT0, VBUSVLDEXT0); + for (tmp = data->pre; tmp->offset != UINT_MAX; tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val); for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { if (hsphy->update_seq_cfg[i].need_update) @@ -441,28 +466,8 @@ static int qcom_snps_hsphy_init(struct phy *phy) hsphy->update_seq_cfg[i].value); } - qcom_snps_hsphy_write_mask(hsphy->base, - USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, - VREGBYPASS, VREGBYPASS); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, - USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, - SLEEPM, SLEEPM); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, - SIDDQ, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, - POR, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, - USB2_SUSPEND_N_SEL, 0); - - qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, - UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + for (tmp = data->post; tmp->offset != UINT_MAX; tmp++) + qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val); hsphy->phy_initialized = true; @@ -495,14 +500,34 @@ static const struct phy_ops qcom_snps_hsphy_gen_ops = { .owner = THIS_MODULE, }; +static const struct phy_config_data hs_5nm_phy = { + .pre = hs_5nm_phy_pre, + .post = hs_5nm_phy_post, +}; + +static const struct phy_config_data hs_7nm_phy = { + .pre = hs_5nm_phy_pre, + .override = sc7280_snps_7nm_phy, + .post = hs_5nm_phy_post, +}; + static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { - { .compatible = "qcom,sm8150-usb-hs-phy", }, - { .compatible = "qcom,usb-snps-hs-5nm-phy", }, + { + .compatible = "qcom,sm8150-usb-hs-phy", + .data = &hs_5nm_phy, + }, + { + .compatible = "qcom,usb-snps-hs-5nm-phy", + .data = &hs_5nm_phy, + }, { .compatible = "qcom,usb-snps-hs-7nm-phy", - .data = &sc7280_snps_7nm_phy, + .data = &hs_7nm_phy, + }, + { + .compatible = "qcom,usb-snps-femto-v2-phy", + .data = &hs_5nm_phy, }, - { .compatible = "qcom,usb-snps-femto-v2-phy", }, { } }; MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); @@ -541,11 +566,14 @@ static void qcom_snps_hsphy_read_override_param_seq(struct device *dev) s32 val; int ret, i; struct qcom_snps_hsphy *hsphy; - const struct override_param_map *cfg = of_device_get_match_data(dev); + const struct phy_config_data *data = of_device_get_match_data(dev); + const struct override_param_map *cfg; - if (!cfg) + if (!data || !data->override) return; + cfg = data->override; + hsphy = dev_get_drvdata(dev); for (i = 0; cfg[i].prop_name != NULL; i++) { -- 2.34.1